200
CHAPTER 13 SERIAL INTERFACE (UART0)
Preliminary User’s Manual U13420EJ2V0UM00
Table 13-3. Relationship between Main System Clock and Baud Rate (2/2)
Baud Rate
f
X
= 2.000 MHz
f
X
= 1.000 MHz
(bps)
BRGC0
ERR (%)
BRGC0
ERR (%)
75
9AH
0.16
8AH
0.16
100
92H
1.36
82H
1.36
150
8AH
0.16
7AH
0.16
300
7AH
0.16
6AH
0.16
600
6AH
0.16
5AH
0.16
1200
5AH
0.16
4AH
0.16
2400
4AH
0.16
3AH
0.16
4800
3AH
0.16
2AH
0.16
9600
2AH
0.16
1AH
0.16
19200
1AH
0.16
–
–
312500
10H
0
–
–
Remark
f
X
: Main system clock oscillation frequency
Figure 13-5. Error Tolerance (when k = 0), Including Sampling Errors
Remark
T: 5-bit counter’s source clock cycle
Baud rate error tolerance (when k = 0) =
±
15.5
×
100 = 4.8438 (%)
320
Basic timing
(clock cycle T)
START
D0
D7
P
STOP
High-speed clock
(clock cycle T’)
enabling normal
reception
START
D0
D7
P
STOP
Low-speed clock
(clock cycle T”)
enabling normal
reception
START
D0
D7
P
STOP
32T
64T
256T
288T
320T
352T
Ideal
sampling
point
304T
336T
30.45T
60.9T
304.5T
15.5T
15.5T
0.5T
Sampling error
33.55T
67.1T
301.95T
335.5T
Содержание mPD780065 Series
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