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CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U16035EJ1V0UM
Cautions 1. When using the main system clock oscillator and a subsystem clock oscillator, wire as
follows in the area enclosed by the broken lines in Figures 5-4 and 5-5 to avoid an adverse
effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as V
SS1
. Do
not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Take special note of the fact that the subsystem clock oscillator is a circuit with low-level
amplification so that current consumption is maintained at low levels.
Figure 5-6 shows examples of incorrect resonator connection.
Figure 5-6. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
X1
IC
X2
X2
IC
X1
PORTn
(n = 0 to 7)
V
SS1
V
SS1
Remark
When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert
resistors in series on the side of XT2.
