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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Preliminary User’s Manual U16035EJ1V0UM
(2) Operation after compare register change during timer count operation
If the value after the 8-bit timer compare register 5n (CR5n) is changed is smaller than the value of 8-bit timer
counter 5n (TM5n), TM5n continues counting, overflows and then restarts counting from 0. Thus, if the value
(M) after CR5n is changed is smaller than the value (N) before it was changed, it is necessary to restart the timer
after changing CR5n.
Figure 7-14. Timing After Change of Compare Register During Timer Count Operation
Count pulse
CR5n
TM5 count value
N
M
X–1
X
FFH
00H
01H
02H
Caution
Except when the TI5n input is selected, always set TCE5n = 0 before setting the stop state.
Remarks 1. N > X > M
2. n = 0, 1
(3) TM5n (n = 0, 1) reading during timer operation
When reading TM5n during operation, select count clock having high/low level waveform longer than two cycles
of CPU clock because count clock stops temporary. For example, in the case where CPU clock (f
CPU
) is f
X
, when
the selected count clock is f
X
/4 or below, it can be read.
Remark
n = 0, 1
