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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0
Preliminary User’s Manual U16035EJ1V0UM
(4) Prescaler mode register 0 (PRM0)
This register is used to set 16-bit timer counter 0 (TM0) count clock and TI00, TI01 input valid edges.
PRM0 is set by an 8-bit memory manipulation instruction.
RESET input sets PRM0 value to 00H.
Figure 6-5. Format of Prescaler Mode Register 0 (PRM0)
Address: FF61H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
PRM0
ES11
ES10
ES01
ES00
0
0
PRM01
PRM00
ES11
ES10
TI01 valid edge selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES01
ES00
TI00 valid edge selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
PRM01
PRM00
Count clock selection
0
0
f
X
(8.38 MHz)
0
1
f
X
/2
2
(2.09 MHz)
1
0
f
X
/2
6
(131 kHz)
1
1
TI00 valid edge
Note
Note
The external clock requires a pulse two times longer than internal clock (f
X
/2
3
).
Cautions 1. If the valid edge of TI00 is to be set to the count clock, do not set the clear & start mode
and the capture trigger at the valid edge of TI00.
Moreover, do not use the P70/TI00/TO0 pins as timer outputs (TO0).
2. Always set data to PRM0 after stopping the timer operation.
3. If the TI00 or TI01 pin is high level immediately after system reset, the rising edge is
immediately detected after the rising edge or both the rising and falling edges are set as
the valid edge(s) of the TI00 pin or TI01 pin to enable the operation of the 16-bit timer counter
0 (TM0). Please be careful when pulling up the TI00 pin or the TI01 pin. However, when re-
enabling operation after the operation has been stopped once, the rising edge is not
detected.
Remarks 1.
f
X
: Main system clock oscillation frequency
2.
TI00, TI01: 16-bit timer/event counter input pin
3.
Figures in parentheses are for operation with f
X
= 8.38 MHz.
