3.0 Functional Description
(Continued)
pins ST0 and ST1 to keep track of the sequence (protocol)
established for the instruction being executed. This is nec-
essary in a virtual memory environment, allowing the FPU to
retry an aborted instruction.
3.4.1 Bus Cycles
A bus cycle is initiated by the CPU, which asserts the proper
status on ST0 and ST1 and pulses SPC low. ST0 and ST1
are sampled by the FPU on the leading (falling) edge of the
SPC pulse. If the transfer is from the FPU (a slave processor
read cycle), the FPU asserts data on the data bus for the
duration of the SPC pulse. If the transfer is to the FPU (a
slave processor write cycle), the FPU latches data from the
data bus on the trailing (rising) edge of the SPC pulse.
Fig-
ures 3-5 and 3-6 illustrate these sequences.
The direction of the transfer and the role of the bidirectional
SPC line are determined by the instruction protocol being
performed. SPC is always driven by the CPU during slave
processor bus cycles. Protocol sequences for each instruc-
tion are given in Section 3.5.
3.4.2 Operand Transfer Sequences
An operand is transferred in one or more bus cycles. A 1-
byte operand is transferred on the least significant byte of
the data bus (D0 – D7). A 2-byte operand is transferred on
the entire bus. A 4-byte or 8-byte operand is transferred in
consecutive bus cycles, least significant word first.
3.5 INSTRUCTION PROTOCOLS
3.5.1 General Protocol Sequence
Slave Processor instructions have a three-byte Basic In-
struction field, consisting of an ID byte followed by an Oper-
ation Word. See Section 2.2.3 for FPU instruction encod-
ings. The ID Byte has three functions:
1) It identifies the instruction to the CPU as being a Slave
Processor instruction.
2) It specifies which Slave Processor will execute it.
3) It determines the format of the following Operation Word
of the instruction.
Upon receiving a Slave Processor instruction, the CPU initi-
ates the sequence outlined in Table 3-2. While applying
Status Code 11 (Broadcast ID. Table 3-1), the CPU trans-
fers the ID Byte on the least significant half of the Data Bus
(D0 – D7). All Slave Processors input this byte and decode it.
The Slave Processor selected by the ID Byte is activated,
and from this point the CPU is communicating only with it. If
any other slave protocol was in progress (e.g., an aborted
Slave instruction), this transfer cancels it.
The CPU next sends the Operation Word while applying
Status Code 01 (Transfer Slave Operand, Table 3-1). Upon
receiving it, the FPU decodes it, and at this point both the
CPU and the FPU are aware of the number of operands to
be transferred and their sizes. The Operation Word is
swapped on the Data Bus; that is, bits 0 – 7 appear on pins
D8 – D15, and bits 8 – 15 appear on pins D0 – D7.
TL/EE/5234 – 16
Note 1:
FPU samples CPU status here.
FIGURE 3-5. Slave Processor Read Cycle
TL/EE/5234 – 17
Note 1:
FPU samples CPU status here.
Note 2:
FPU samples data bus here.
FIGURE 3-6. Slave Processor Write Cycle
11
