National Semiconductor NS32081-10, Руководство пользователя, Страница: 15 / 18

4.0 Device Specifications
(Continued)
4.4.2 Timing Tables
4.4.2.1 Output Signal Propagation Delays
Maximum times assume capacitive loading of 100 pF.
Name Figure Description
Reference/
NS32081-10 NS32081-15
Units
Conditions
Min Max Min Max
t
Dv
4-7 Data Valid After SPC L.E. 45 30 ns
t
Df
4-7 D
0
– D
15
Floating After SPC T.E. 50 2 35 ns
t
SPCFw
4-9 SPC Pulse Width At 0.8V
t
CLKp
b
50 t
CLKp
a
50 t
CLKp
b
40 t
CLKp
a
40 ns
from FPU (Both Edges)
t
SPCFl
4-9 SPC Output Active After CLK R.E. 55 38 ns
t
SPCFh
4-9 SPC Output Inactive After CLK R.E. 55 38 ns
t
SPCFnf
4-9 SPC Output After CLK F.E.
45 35 ns
Nonforcing
4.4.2.2 Input Signal Requirements
Name Figure Description
Reference/
Min Max Min Max Units
Conditions
t
PWR
4-5 Power Stable to After V
CC
50 50 m s
RST R.E. Reaches 4.5V
t
RSTw
4-6 RST Pulse Width At 0.8V
64 64 t
CLKp
(Both Edges)
t
Ss
4-7 Status (ST0 – ST1) Before SPC L.E.
50 33 ns
Setup
t
Sh
4-7 Status (ST0 – ST1) After SPC L.E.
40 35 ns
Hold
t
Ds
4-8 D0 – D15 Setup Time Before SPC T.E. 40 30 ns
t
Dh
4-8 D0 – D15 Hold Time After SPC T.E. 50 35 ns
t
SPCw
4-7 SPC Pulse Width At 0.8V
70 50 ns
from CPU (Both Edges)
t
SPCs
4-7 SPC Input Active Before CLK R.E. 40 35 ns
t
SPCh
4-7 SPC Input Inactive After CLK R.E. 0 0 ns
t
RSTs
4-10 RST Setup Before CLK F.E. 10 10 ns
t
RSTh
4-10 RST R.E. Delay After CLK R.E. 0 0 ns
4.4.2.3 Clocking Requirements
Name Figure Description
Reference/
Min Max Min Max Units
Conditions
t
CLKh
4-4 Clock High Time At 2.0V
42 1000 27 1000 ns
(Both Edges)
t
CLKl
4-4 Clock Low Time At 0.8V
42 1000 27 1000 ns
(Both Edges)
t
CLKp
4-4 Clock Period CLK R.E. to Next
100 2000 66 ns
CLK R.E.
15