1.0 Product Introduction
(Continued)
TABLE 1-3. Normalized Number Ranges
Single Precision
Double Precision
Most Positive
2
127
c
(2
b
2
b
23
)
2
1023
c
(2
b
2
b
52
)
e
3.40282346
c
10
38
e
1.7976931348623157
c
10
308
Least Positive
2
b
126
2
b
1022
e
1.17549436
c
10
b
38
e
2.2250738585072014
c
10
b
308
Least Negative
b
(2
b
126
)
b
(2
b
1022
)
e b
1.17549436
c
10
b
38
e b
2.2250738585072014
c
10
b
308
Most Negative
b
2
127
c
(2
b
2
b
23
)
b
2
1023
c
(2
b
2
b
52
)
e b
3.40282346
c
10
38
e b
1.7976931348623157
c
10
308
Note:
The values given are extended one full digit beyond their represented accuracy to help in generating rounding and conversion algorithms.
1.1.4 Integers
In addition to performing floating-point arithmetic, the
NS32081 FPU performs conversions between integer and
floating-point data types. Integers are accepted or generat-
ed by the FPU as two’s complement values of byte (8 bits),
word (16 bits) or double word (32 bits) length.
1.1.5 Memory Representations
The NS32081 FPU does not directly access memory. How-
ever, it is cooperatively involved in the execution of a set of
two-address instructions with its Series 32000 Family CPU.
The CPU determines the representation of operands in
memory.
In the Series 32000 family of CPUs, operands are stored in
memory with the least significant byte at the lowest byte
address. The only exception to this rule is the Immediate
addressing mode, where the operand is held (within the in-
struction format) with the most significant byte at the lowest
address.
2.0 Architectural Description
2.1 PROGRAMMING MODEL
The Series 32000 architecture includes nine registers that
are implemented on the NS32081 Floating-Point Unit (FPU).
TL/EE/5234 – 4
FIGURE 2-1. Register Set
2.1.1 Floating-Point Registers
There are eight registers (F0 – F7) on the NS32081 FPU for
providing high-speed access to floating-point operands.
Each is 32 bits long. A floating-point register is referenced
whenever a floating-point instruction uses the Register ad-
dressing mode (Section 2.2.2) for a floating-point operand.
All other Register mode usages (i.e., integer operands) refer
to the General Purpose Registers (R0 – R7) of the CPU, and
the FPU transfers the operand as if it were in memory.
When the Register addressing mode is specified for a dou-
ble precision (64-bit) operand, a pair of registers holds the
operand. The programmer must specify the even register of
the pair. The even register contains the least significant half
of the operand and the next consecutive register contains
the most significant half.
2.1.2 Floating-Point Status Register (FSR)
The Floating-Point Status Register (FSR) selects operating
modes and records any exceptional conditions encountered
during execution of a floating-point operation.
Figure 2-2
shows the format of the FSR.
TL/EE/5234 – 5
FIGURE 2-2. The Floating-Point Status Register
2.1.2.1 FSR Mode Control Fields
The FSR mode control fields select FPU operation modes.
The meanings of the FSR mode control bits are given be-
low.
Rounding Mode (RM):
Bits 7 and 8. This field selects the
rounding method. Floating-point results are rounded when-
ever they cannot be exactly represented. The rounding
modes are:
00 Round to nearest value. The value which is nearest to
the exact result is returned. If the result is exactly half-
way between the two nearest values the even value
(LSB
e
0) is returned.
01 Round toward zero. The nearest value which is closer to
zero or equal to the exact result is returned.
5
