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2.0 Architectural Description

(Continued)

Comparison

The Compare instruction compares two floating-point val-
ues, sending the result to the CPU PSR Z and N bits for use
as condition codes. See

Figure 3-7 . The Z bit is set if the

gen1 and gen2 operands are equal; it is cleared otherwise.
The N bit is set if the gen1 operand is greater than the gen2
operand; it is cleared otherwise. The CPU PSR L bit is un-
conditionally cleared. Positive and negative zero are consid-
ered equal.

Format

Op

Instruction

Description

11

0010

CMPf

gen1, gen2

Compare gen1
to gen2.

Floating-Point Status Register Access

The following instructions load and store the FSR as a 32-
bit integer.

Format

Op

Instruction

Description

9

001

LFSR

gen1

Load FSR

9

110

SFSR

gen2

Store FSR

2.3 TRAPS

Upon detecting an exceptional condition in executing a
floating-point instruction, the NS32081 FPU requests a trap
by setting the Q bit of the status word transferred during the
slave protocol (Section 3.5). The CPU responds by perform-
ing a trap using a default vector value of 3. See the Series
32000 Instruction Set Reference Manual and the applicable
CPU data sheet for trap service details.

A trapped floating-point instruction returns no result, and
does not affect the CPU Processor Status Register (PSR).
The FPU displays the reason for the trap in the Trap Type
(TT) field of the FSR (Section 2.1.2.2).

3.0 Functional Description

3.1 POWER AND GROUNDING

The NS32081 requires a single 5V power supply, applied on
pin 24 (V

CC

). See DC Electrical Characteristics table.

Grounding connections are made on two pins. Logic Ground
(GNDL, pin 12) is the common pin for on-chip logic, and
Buffer Ground (GNDB, pin 13) is the common pin for the
output drivers. For optimal noise immunity, it is recommend-
ed that GNDL be attached through a single conductor di-
rectly to GNDB, and that all other grounding connections be
made only to GNDB, as shown below (

Figure 3-1 ).

TL/EE/5234 – 13

FIGURE 3-1. Recommended Supply Connections

3.2 CLOCKING

The NS32081 FPU requires a single-phase TTL clock input
on its CLK pin (pin 14). When the FPU is connected to a
Series 32000 CPU, the CLK signal is provided from the
CTTL pin of the NS32201 Timing Control Unit.

3.3 RESETTING

The RST pin serves as a reset for on-chip logic. The FPU
may be reset at any time by pulling the RST pin low for at
least 64 clock cycles. Upon detecting a reset, the FPU ter-
minates instruction processing, resets its internal logic, and
clears the FSR to all zeroes.

On application of power, RST must be held low for at least
50

m

s after V

CC

is stable. This ensures that all on-chip volt-

ages are completely stable before operation. See

Figures 3-2

and

3-3.

TL/EE/5234 – 14

FIGURE 3-2. Power-On Reset Requirements

TL/EE/5234 – 15

FIGURE 3-3. General Reset Timing

3.4 BUS OPERATION

Instructions and operands are passed to the NS32081 FPU
with slave processor bus cycles. Each bus cycle transfers
either one byte (8 bits) or one word (16 bits) to or from the
FPU. During all bus cycles, the SPC line is driven by the
CPU as an active low data strobe, and the FPU monitors

TL/EE/5234 – 2

FIGURE 3-4. System Connection Diagram

10

Содержание NS32081-10

Страница 1: ... archi tecture and powerful addressing modes of the Series 32000 micro processor family Features Y Eight on chip data registers Y 32 bit and 64 bit operations Y Supports proposed IEEE standard for binary floating point arithmetic Task P754 Y Directly compatible with NS32016 NS32008 and NS32032 CPUs Y High speed XMOSTM technology Y Single 5V supply Y 24 pin dual in line package Block Diagram TL EE ...

Страница 2: ...t Instruction Set 2 3 Traps 3 0 FUNCTIONAL DESCRIPTION 3 1 Power and Grounding 3 2 Clocking 3 3 Resetting 3 0 FUNCTIONAL DESCRIPTION Continued 3 4 Bus Operation 3 4 1 Bus Cycles 3 4 2 Operand Transfer Sequences 3 5 Instruction Protocols 3 5 1 General Protocol Sequence 3 5 2 Floating Point Protocols 4 0 DEVICE SPECIFICATIONS 4 1 Pin Descriptions 4 1 1 Supplies 4 1 2 Input Signals 4 1 3 Input Output...

Страница 3: ...PackageÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4 1 Timing Specification Standard Signal Valid After Clock Edge ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4 2 Timing Specification Standard Signal Valid Before Clock Edge ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4 3 Clock Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ...

Страница 4: ...r positive or negative as shown in Table 1 2 TABLE 1 2 Sample E Fields E Field F Field Represented Value 011 110 100 0 1 5c2b1 e 0 75 011 111 100 0 1 5c20 e 1 50 100 000 100 0 1 5c21 e 3 00 Two values of the E field are not exponents 11 11 sig nals a reserved operand Section 2 1 3 00 00 repre sents the number zero if the F field is also all zeroes other wise it signals a reserved operand The S bit...

Страница 5: ... Point Unit FPU TL EE 5234 4 FIGURE 2 1 Register Set 2 1 1 Floating Point Registers There are eight registers F0 F7 on the NS32081 FPU for providing high speed access to floating point operands Each is 32 bits long A floating point register is referenced whenever a floating point instruction uses the Register ad dressing mode Section 2 2 2 for a floating point operand All other Register mode usage...

Страница 6: ...e this condi tion 011 Divide by zero An attempt has been made to divide a non zero floating point number by zero Dividing zero by zero is considered an Invalid Operation instead below 100 Illegal Instruction Two undefined floating point instruc tion forms are detected by the FPU as being illegal The binary formats causing this trap are xxxxxxxxxx0011xx10111110 xxxxxxxxxx1001xx10111110 101 Invalid ...

Страница 7: ...n the instruction which acts upon that variable Extraneous data movement is therefore mini mized Series 32000 Addressing Modes fall into nine basic types Register In floating point instructions these addressing modes refer to a Floating Point Register F0 F7 if the op erand is of a floating point type Otherwise a CPU General Purpose Register R0 R7 is referenced See Section 2 1 1 Register Relative A...

Страница 8: ...k memory disp SP SP0 or SP1 as selected in PSR 11010 Static memory disp SB 11011 Program memory adisp MEMORY RELATIVE 10000 Frame memory relative disp2 disp1 FP Disp2aPointer Pointer found at 10001 Stack memory relative disp2 disp1 SP address Disp1aRegister SP is 10010 Static memory relative disp2 disp1 SB either SP0 or SP1 as selected in PSR IMMEDIATE 10100 Immediate value None Operand is issued ...

Страница 9: ... indicates a choice of addressing mode expressions This choice affects the bina ry pattern in the corresponding gen1 or gen2 field of the instruction format Figure 2 6 Refer to Table 2 1 for the options available and their patterns Further details of the exact operations performed by each instruction are found in the Series 32000 Instruction Set Reference Manual Movement and Conversion The followi...

Страница 10: ...wer supply applied on pin 24 VCC See DC Electrical Characteristics table Grounding connections are made on two pins Logic Ground GNDL pin 12 is the common pin for on chip logic and Buffer Ground GNDB pin 13 is the common pin for the output drivers For optimal noise immunity it is recommend ed that GNDL be attached through a single conductor di rectly to GNDB and that all other grounding connection...

Страница 11: ...CTION PROTOCOLS 3 5 1 General Protocol Sequence Slave Processor instructions have a three byte Basic In struction field consisting of an ID byte followed by an Oper ation Word See Section 2 2 3 for FPU instruction encod ings The ID Byte has three functions 1 It identifies the instruction to the CPU as being a Slave Processor instruction 2 It specifies which Slave Processor will execute it 3 It det...

Страница 12: ...n The instructions are referenced by their mnemonics For the bit encodings of each instruction see Section 2 2 3 The Operand Class columns give the Access Classes for each general operand defining how the addressing modes are interpreted by the CPU see Series 32000 Instruction Set Reference Manual The Operand Issued columns show the sizes of the oper ands issued to the Floating Point Unit by the C...

Страница 13: ... the FPU to signal completion of an operation Section 3 5 1 Must be held high with an external pull up resistor while floating Data Bus D0 D15 16 bit bus for data transfer D0 is the least significant bit Section 3 4 4 2 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias 0 C to a70 C Storage Temperature b65 C to a150 C All Input or Output Voltages with Respect to GND b0 5V to a7 0V Power Dissipation 1...

Страница 14: ...the input and output signals as illustrated in Figures 4 2 and 4 3 unless specifically stated otherwise ABBREVIATIONS L E Ð Leading Edge T E Ð Trailing Edge R E Ð Rising Edge F E Ð Falling Edge TL EE 5234 26 FIGURE 4 2 Timing Specification Standard Signal Valid After Clock Edge TL EE 5234 27 FIGURE 4 3 Timing Specification Standard Signal Valid Before Clock Edge 14 ...

Страница 15: ...ts Conditions tPWR 4 5 Power Stable to After VCC 50 50 ms RST R E Reaches 4 5V tRSTw 4 6 RST Pulse Width At 0 8V 64 64 tCLKp Both Edges tSs 4 7 Status ST0 ST1 Before SPC L E 50 33 ns Setup tSh 4 7 Status ST0 ST1 After SPC L E 40 35 ns Hold tDs 4 8 D0 D15 Setup Time Before SPC T E 40 30 ns tDh 4 8 D0 D15 Hold Time After SPC T E 50 35 ns tSPCw 4 7 SPC Pulse Width At 0 8V 70 50 ns from CPU Both Edges...

Страница 16: ...n Reset TL EE 5234 21 FIGURE 4 6 Non Power On Reset TL EE 5234 22 FIGURE 4 7 Read Cycle from FPU Note SPC pulse must be nominally 1 clock wide when writing into FPU TL EE 5234 23 FIGURE 4 8 Write Cycle to FPU Note SPC pulse may also be 2 clocks wide but its edges must meet the tSPCs and tSPCh requirements with respect to CLK 16 ...

Страница 17: ...PC Pulse from FPU TL EE 5234 25 FIGURE 4 10 RST Release Timing Note The rising edge of RST must occur while CLK is high as shown Physical Dimensions inches millimeters Ceramic Dual In Line Package D Order Number NS32081D 10 or NS32081D 15 NS Package Number D24C 17 ...

Страница 18: ...d in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax a49 0 180 530 85 86 13th Floor St...

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