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2.0 Architectural Description

(Continued)

and contains the opcode and up to two 5-bit General Ad-
dressing Mode (Gen) fields. Following the Basic Instruction
field is a set of optional extensions, which may appear de-
pending on the instruction and the addressing modes se-
lected.

The only form of extension issued to the NS32081 FPU is
an Immediate operand. Other extensions are used only by
the CPU to reference memory operands needed by the
FPU.

Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before index-
ing. See

Figure 2-4 .

Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the select-
ed addressing modes. Each Disp/lmm field may contain
one or two displacements, or one immediate value. The size
of a Displacement field is encoded within the top bits of that
field, as shown in

Figure 2-5 , with the remaining bits inter-

preted as a signed (two’s complement) value. The size of an
immediate value is determined from the Opcode field. Both
Displacement and Immediate fields are stored most signifi-
cant byte first.

Some non-FPU instructions require additional, ‘‘implied’’ im-
mediates and/or displacements, apart from those associat-
ed with addressing modes. Any such extensions appear at
the end of the instruction, in the order that they appear with-
in the list of operands in the instruction definition.

2.2.2 Addressing Modes

The Series 32000 Family CPUs generally access an oper-
and by calculating its Effective Address based on informa-
tion available when the operand is to be accessed. The
method to be used in performing this calculation is specified
by the programmer as an ‘‘addressing mode.’’

Addressing modes in the Series 32000 family are designed
to optimally support high-level language accesses to vari-
ables. In nearly all cases, a variable access requires only
one addressing mode within the instruction which acts upon
that variable. Extraneous data movement is therefore mini-
mized.

Series 32000 Addressing Modes fall into nine basic types:

Register:

In floating-point instructions, these addressing

modes refer to a Floating-Point Register (F0 – F7) if the op-
erand is of a floating-point type. Otherwise, a CPU General
Purpose Register (R0 – R7) is referenced. See Section 2.1.1.

Register Relative:

A CPU General Purpose Register con-

tains an address to which is added a displacement value
from the instruction, yielding the Effective Address of the
operand in memory.

TL/EE/5234 – 7

FIGURE 2-4. Index Byte Format

Memory Space:

Identical to Register Relative above, ex-

cept that the register used is one of the dedicated CPU
registers PC, SP, SB or FP. These registers point to data
areas generally needed by high-level languages.

Memory Relative:

A pointer variable is found within the

memory space pointed to by the CPU SP, SB or FP register.
A displacement is added to that pointer to generate the Ef-
fective Address of the operand.

Immediate:

The operand is encoded within the instruction.

This addressing mode is not allowed if the operand is to be
written. Floating-point operands as well as integer operands
may be specified using Immediate mode.

Absolute:

The address of the operand is specified by a

Displacement field in the instruction.

External:

A pointer value is read from a specified entry of

the current Link Table. To this pointer value is added a dis-
placement, yielding the Effective Address of the operand.

Top of Stack:

The currently-selected CPU Stack Pointer

(SP0 or SP1) specifies the location of the operand. The op-
erand is pushed or popped, depending on whether it is writ-
ten or read.

Scaled Index:

Although encoded as an addressing mode,

Scaled Indexing is an option on any addressing mode ex-
cept Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any Gen-
eral Purpose Register by 1, 2, 4 or 8 and adding it into the
total, yielding the final Effective Address of the operand.

The following table, Table 2-1, is a brief summary of the
addressing modes. For a complete description of their ac-
tions, see the Series 32000 Instruction Set Reference Man-
ual.

TL/EE/5234 – 10

FIGURE 2-5. Displacement Encodings

7

Содержание NS32081-10

Страница 1: ... archi tecture and powerful addressing modes of the Series 32000 micro processor family Features Y Eight on chip data registers Y 32 bit and 64 bit operations Y Supports proposed IEEE standard for binary floating point arithmetic Task P754 Y Directly compatible with NS32016 NS32008 and NS32032 CPUs Y High speed XMOSTM technology Y Single 5V supply Y 24 pin dual in line package Block Diagram TL EE ...

Страница 2: ...t Instruction Set 2 3 Traps 3 0 FUNCTIONAL DESCRIPTION 3 1 Power and Grounding 3 2 Clocking 3 3 Resetting 3 0 FUNCTIONAL DESCRIPTION Continued 3 4 Bus Operation 3 4 1 Bus Cycles 3 4 2 Operand Transfer Sequences 3 5 Instruction Protocols 3 5 1 General Protocol Sequence 3 5 2 Floating Point Protocols 4 0 DEVICE SPECIFICATIONS 4 1 Pin Descriptions 4 1 1 Supplies 4 1 2 Input Signals 4 1 3 Input Output...

Страница 3: ...PackageÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4 1 Timing Specification Standard Signal Valid After Clock Edge ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4 2 Timing Specification Standard Signal Valid Before Clock Edge ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4 3 Clock Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ...

Страница 4: ...r positive or negative as shown in Table 1 2 TABLE 1 2 Sample E Fields E Field F Field Represented Value 011 110 100 0 1 5c2b1 e 0 75 011 111 100 0 1 5c20 e 1 50 100 000 100 0 1 5c21 e 3 00 Two values of the E field are not exponents 11 11 sig nals a reserved operand Section 2 1 3 00 00 repre sents the number zero if the F field is also all zeroes other wise it signals a reserved operand The S bit...

Страница 5: ... Point Unit FPU TL EE 5234 4 FIGURE 2 1 Register Set 2 1 1 Floating Point Registers There are eight registers F0 F7 on the NS32081 FPU for providing high speed access to floating point operands Each is 32 bits long A floating point register is referenced whenever a floating point instruction uses the Register ad dressing mode Section 2 2 2 for a floating point operand All other Register mode usage...

Страница 6: ...e this condi tion 011 Divide by zero An attempt has been made to divide a non zero floating point number by zero Dividing zero by zero is considered an Invalid Operation instead below 100 Illegal Instruction Two undefined floating point instruc tion forms are detected by the FPU as being illegal The binary formats causing this trap are xxxxxxxxxx0011xx10111110 xxxxxxxxxx1001xx10111110 101 Invalid ...

Страница 7: ...n the instruction which acts upon that variable Extraneous data movement is therefore mini mized Series 32000 Addressing Modes fall into nine basic types Register In floating point instructions these addressing modes refer to a Floating Point Register F0 F7 if the op erand is of a floating point type Otherwise a CPU General Purpose Register R0 R7 is referenced See Section 2 1 1 Register Relative A...

Страница 8: ...k memory disp SP SP0 or SP1 as selected in PSR 11010 Static memory disp SB 11011 Program memory adisp MEMORY RELATIVE 10000 Frame memory relative disp2 disp1 FP Disp2aPointer Pointer found at 10001 Stack memory relative disp2 disp1 SP address Disp1aRegister SP is 10010 Static memory relative disp2 disp1 SB either SP0 or SP1 as selected in PSR IMMEDIATE 10100 Immediate value None Operand is issued ...

Страница 9: ... indicates a choice of addressing mode expressions This choice affects the bina ry pattern in the corresponding gen1 or gen2 field of the instruction format Figure 2 6 Refer to Table 2 1 for the options available and their patterns Further details of the exact operations performed by each instruction are found in the Series 32000 Instruction Set Reference Manual Movement and Conversion The followi...

Страница 10: ...wer supply applied on pin 24 VCC See DC Electrical Characteristics table Grounding connections are made on two pins Logic Ground GNDL pin 12 is the common pin for on chip logic and Buffer Ground GNDB pin 13 is the common pin for the output drivers For optimal noise immunity it is recommend ed that GNDL be attached through a single conductor di rectly to GNDB and that all other grounding connection...

Страница 11: ...CTION PROTOCOLS 3 5 1 General Protocol Sequence Slave Processor instructions have a three byte Basic In struction field consisting of an ID byte followed by an Oper ation Word See Section 2 2 3 for FPU instruction encod ings The ID Byte has three functions 1 It identifies the instruction to the CPU as being a Slave Processor instruction 2 It specifies which Slave Processor will execute it 3 It det...

Страница 12: ...n The instructions are referenced by their mnemonics For the bit encodings of each instruction see Section 2 2 3 The Operand Class columns give the Access Classes for each general operand defining how the addressing modes are interpreted by the CPU see Series 32000 Instruction Set Reference Manual The Operand Issued columns show the sizes of the oper ands issued to the Floating Point Unit by the C...

Страница 13: ... the FPU to signal completion of an operation Section 3 5 1 Must be held high with an external pull up resistor while floating Data Bus D0 D15 16 bit bus for data transfer D0 is the least significant bit Section 3 4 4 2 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias 0 C to a70 C Storage Temperature b65 C to a150 C All Input or Output Voltages with Respect to GND b0 5V to a7 0V Power Dissipation 1...

Страница 14: ...the input and output signals as illustrated in Figures 4 2 and 4 3 unless specifically stated otherwise ABBREVIATIONS L E Ð Leading Edge T E Ð Trailing Edge R E Ð Rising Edge F E Ð Falling Edge TL EE 5234 26 FIGURE 4 2 Timing Specification Standard Signal Valid After Clock Edge TL EE 5234 27 FIGURE 4 3 Timing Specification Standard Signal Valid Before Clock Edge 14 ...

Страница 15: ...ts Conditions tPWR 4 5 Power Stable to After VCC 50 50 ms RST R E Reaches 4 5V tRSTw 4 6 RST Pulse Width At 0 8V 64 64 tCLKp Both Edges tSs 4 7 Status ST0 ST1 Before SPC L E 50 33 ns Setup tSh 4 7 Status ST0 ST1 After SPC L E 40 35 ns Hold tDs 4 8 D0 D15 Setup Time Before SPC T E 40 30 ns tDh 4 8 D0 D15 Hold Time After SPC T E 50 35 ns tSPCw 4 7 SPC Pulse Width At 0 8V 70 50 ns from CPU Both Edges...

Страница 16: ...n Reset TL EE 5234 21 FIGURE 4 6 Non Power On Reset TL EE 5234 22 FIGURE 4 7 Read Cycle from FPU Note SPC pulse must be nominally 1 clock wide when writing into FPU TL EE 5234 23 FIGURE 4 8 Write Cycle to FPU Note SPC pulse may also be 2 clocks wide but its edges must meet the tSPCs and tSPCh requirements with respect to CLK 16 ...

Страница 17: ...PC Pulse from FPU TL EE 5234 25 FIGURE 4 10 RST Release Timing Note The rising edge of RST must occur while CLK is high as shown Physical Dimensions inches millimeters Ceramic Dual In Line Package D Order Number NS32081D 10 or NS32081D 15 NS Package Number D24C 17 ...

Страница 18: ...d in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax a49 0 180 530 85 86 13th Floor St...

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