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1.0 Product Introduction
The NS32081 Floating-Point Unit (FPU) provides high
speed floating-point operations for the Series 32000 family,
and is fabricated using National high-speed XMOS technol-
ogy. It operates as a slave processor for transparent expan-
sion of the Series 32000 CPU’s basic instruction set. The
FPU can also be used with other microprocessors as a pe-
ripheral device by using additional TTL interface logic. The
NS32081 is compatible with the IEEE Floating-Point For-
mats by means of its hardware and software features.
1.1 OPERAND FORMATS
The NS32081 FPU operates on two floating-point data
typesÐsingle precision (32 bits) and double precision (64
bits). Floating-point instruction mnemonics use the suffix F
(Floating) to select the single precision data type, and the
suffix L (Long Floating) to select the double precision data
type.
A floating-point number is divided into three fields, as shown
in
Figure 1-1 .
The F field is the fractional portion of the represented num-
ber. In Normalized numbers (Section 1.1.1), the binary point
is assumed to be immediately to the left of the most signifi-
cant bit of the F field, with an implied 1 bit to the left of the
binary point. Thus, the F field represents values in the range
1.0
s
x
s
2.0.
TABLE 1-1. Sample F Fields
F Field
Binary Value
Decimal Value
000 . . . 0
1.000 . . . 0
1.000 . . . 0
010 . . . 0
1.010 . . . 0
1.250 . . . 0
100 . . . 0
1.100 . . . 0
1.500 . . . 0
110 . . . 0
1.110 . . . 0
1.750 . . . 0
u
Implied Bit
The E field contains an unsigned number that gives the bi-
nary exponent of the represented number. The value in the
E field is biased; that is, a constant bias value must be sub-
tracted from the E field value in order to obtain the true
exponent. The bias value is 011 . . . 11
2
, which is either 127
(single precision) or 1023 (double precision). Thus, the true
exponent can be either positive or negative, as shown in
Table 1-2.
TABLE 1-2. Sample E Fields
E Field
F Field
Represented Value
011 . . . 110
100 . . . 0
1.5
c
2
b
1
e
0.75
011 . . . 111
100 . . . 0
1.5
c
2
0
e
1.50
100 . . . 000
100 . . . 0
1.5
c
2
1
e
3.00
Two values of the E field are not exponents. 11 . . . 11 sig-
nals a reserved operand (Section 2.1.3). 00 . . . 00 repre-
sents the number zero if the F field is also all zeroes, other-
wise it signals a reserved operand.
The S bit indicates the sign of the operand. It is 0 for posi-
tive and 1 for negative. Floating-point numbers are in sign-
magnitude form, that is, only the S bit is complemented in
order to change the sign of the represented number.
1.1.1 Normalized Numbers
Normalized numbers are numbers which can be expressed
as floating-point operands, as described above, where the E
field is neither all zeroes nor all ones.
The value of a Normalized number can be derived by the
formula:
(
b
1)
S
c
2
(E-Bias)
c
(1
a
F)
The range of Normalized numbers is given in Table 1-3.
1.1.2 Zero
There are two representations for zeroÐpositive and nega-
tive. Positive zero has all-zero F and E fields, and the S bit is
zero. Negative zero also has all-zero F and E fields, but its S
bit is one.
1.1.3 Reserved Operands
The proposed IEEE Standard for Binary Floating-Point Arith-
metic (Task P754) provides for certain exceptional forms of
floating-point operands. The NS32081 FPU treats these
forms as reserved operands. The reserved operands are:
#
Positive and negative infinity
#
Not-a-Number (NaN) values
#
Denormalized numbers
Both Infinity and NaN values have all ones in their E fields.
Denormalized numbers have all zeroes in their E fields and
non-zero values in their F fields.
The NS32081 FPU causes an Invalid Operation trap (Sec-
tion 2.1.2.2) if it receives a reserved operand, unless the
operation is simply a move (without conversion). The FPU
does not generate reserved operands as results.
Single Precision
31 30
23 22
0
S
E
F
1
8
23
Double Precision
63 62
52 51
0
S
E
F
1
11
52
FIGURE 1-1. Floating-Point Operand Formats
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