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© 1999 National Semiconductor Corporation

http://www.national.com

 

Printed in the U.S.A.

 

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Section I. Introduction 

 

The CLC3790093 Data Capture Board enables simple evaluation
of National Semiconductor’s High Speed Analog to Digital Con-
verters (ADCs) and the Diversity Receiver Chip Set (DRCS). The
Data Capture Board interfaces the outputs of these devices to the
standard serial port available on the back of most Personal
Computers (PCs). We have provided PC software to control the
data capture function and Matlab

 

®

 

 scripts for data analysis.

A block diagram of the evaluation test bed is shown below. 

The Data Capture Board contains a field-programmable gate
array (FPGA) that controls its operation. An EPROM configures
the FPGA after power is applied. The serial interface is provided
by a UART (Universal Asynchronous Receiver/Transmitter), an
oscillator, and a level translator IC. The captured data is stored in
either three 32K x 8 static RAMs (organized into 24-bit words) or
in a FIFO containing 32K 18-bit words. LEDs provide a visual
indication of activity. DIP switches and a jumper configure several
capture functions.

 

Section II. Capturing Data from ADC 
Evaluation Boards 

 

Getting Started

 

To use the Data Capture board to capture data from a National
Semiconductor Analog to Digital converter, you will need the
following hardware, software, and documentation. 

 

CLC-CAPT-PCASM
Data Capture Board User’s Guide

 

Table of Contents

 

I. Introduction
II.  Capturing Data from ADC

 Evaluation 

Boards

III.  Capturing Data from the DRCS 

Evaluation Boards

IV.  Data Analysis using Matlab

 Script 

Files

 

May 1999

Rev 1.0.0

 

CLC-CAPT

-PCASM

Data Capture Boar

d User’

s Guide

CLC5956

Evaluation Board

CLC5958

Evaluation Board

Digital Receiver

ChipSet (DRCS)

Evaluation Board

Data

Capture

Board

National Semiconductor

High-Speed Converter

Evaluation Test Bed

Summary of Contents for Data Capture Board CLC-CAPT-PCASM

Page 1: ...Receiver Transmitter an oscillator and a level translator IC The captured data is stored in either three 32K x 8 static RAMs organized into 24 bit words or in a FIFO containing 32K 18 bit words LEDs...

Page 2: ...n board An amplitude of 10 to 16dBm is recommended Here again the HP 8644B is a good choice Software 1 National Semiconductor Software All of the required software is provided on a CD ROM To install t...

Page 3: ...on board pin 20B The third jumper block J2 is unused Data Capture Board Block Diagram DIP Switches Five of the eight DIP switches are used to configure several capture functions as follows DIP switch...

Page 4: ...e Data Capture Board is powered up and the FPGA is initialized it is on to indicate that the board is ready After all the SRAM data has been output it is off LED 2 This LED is on when captured data is...

Page 5: ...ou start with the default file name and location shown Click on Default and then on OK If you do not have a C temp directory please make one The reason for this is that the Matlab script files for dat...

Page 6: ...configuration menu Select Histogram Debug as shown above and click on OK When the data capture control panel returns you can verify your capture settings by positioning the mouse over the progress bar...

Page 7: ...and Capture Board combination require 5V at 1A 4 An IBM Compatible Personal Computer running Windows 95 Windows 98 or Windows NT with a serial port capable of 115 200 baud 5 Serial data cable to conne...

Page 8: ...on The SRAM is useful for displaying time records of data or collecting contiguous blocks of slower data that have been decimated by the CLC5902 DDC The SRAM is the memory element used for the board s...

Page 9: ...rted Next is a discussion of the Mode functions and the related sub functions MODES There are four primary modes in which to run the data capture system each with its own associated options 1 Capture...

Page 10: ...ta source The DRCS Debug data will be displayed at the 15 bit resolution limit this is also the case for the DRCS 24 bit Serial Out data and the histogram will be centered about 16 384 assuming there...

Page 11: ...ditions The main portion of the noise power is contained in the carrier s immediate sidebands 5KHz Another point of interest is that there are several spectral lines about 75dBFS and 25KHz on either s...

Page 12: ...variable to 0 Setting the Dither variable excludes a lower portion of the spectrum from the FFT analysis and is intended to be used in conjunction with a base band dither signal being present at the...

Page 13: ...13 http www national com CLC CAPT PCASM Evaluation Board Layer 1 CLC CAPT PCASM Evaluation Board Layer 2 CLC CAPT PCASM Evaluation Board Layer 3 CLC CAPT PCASM Evaluation Board Layer 4...

Page 14: ...1 1 1 1 6 287 287 287 1 9 9 1 1 1 1 1 1 1 6 6 287 9 9 9 9 5 9 9 9 9 1 4 5 2 2 5 1 57 4 4 9 4 3 3 1 1 5 5 1 2 9 1 4 1 4 602 9 4 1 4 4 4 4 4 4 9 4 4 1 4 4 1 4 56 1 1 1 1 1 865 21 B 21 6 7 7 7 7 7 7 7 7...

Page 15: ...o perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor National Semicondu...

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