Index
I-2
www.ni.com
F
field, for interlaced video signal, 3-7
FIFO buffer, 3-4
formats supported, A-1
frame
definition, 3-7
frame/field selection, 3-5
functional overview, 3-1 to 3-5
G
gain and offset circuitry, programmable, 3-2
genlock and synchronization circuitry, 3-3
GND signal (table), 4-3
H
hardware overview, 3-1 to 3-9
8-bit ADC and LUT, 3-3
acquisition and region-of-interest
control, 3-4
acquisition modes, 3-9
antichrominance filter, 3-2
block diagram, 3-2
board configuration NVRAM, 3-5
CSYNC mux, 3-3
FIFO buffer, 3-4
functional overview, 3-1 to 3-5
genlock and synchronization
circuitry, 3-3
PCI interface, 3-5
PCLK, HSYNC, VSYNC mux, 3-3
pixel aspect ratio circuitry, 3-3
programmable gain and offset, 3-2
RTSI bus, 3-4
scatter-gather DMA controllers, 3-4
trigger control and mapping circuitry, 3-4
VCO and PLL circuitry, 3-3
video acquisition, 3-5 to 3-8
acquisition window control,
3-6 to 3-7
programming video parameters,
3-7 to 3-8
start conditions, 3-5
video mux, 3-2
horizontal count, 3-6
HSYNC
acquisition window control, 3-6
genlock and synchronization
circuitry, 3-3
PCLK, HSYNC, VSYNC mux, 3-3
HSYNCIN± signal (table), 4-2
I
IMAQ Vision software, 1-5
IMAQ Vision Builder software, 1-5
installation. See also configuration.
procedure for, 2-8 to 2-9
setting up IMAQ system, 2-2 to 2-3
unpacking the PCI/PXI-1408, 2-4
integration with DAQ and motion control, 1-6
interlaced video, 3-8
internal pixel clock specifications, A-3
I/O connector, 4-1 to 4-3
avoiding VIDEO0 connection with BNC
connector, 4-1
custom cable specifications, B-1
pin assignments (figure), 4-2
signal descriptions (table), 4-2 to 4-3
VIDEO0 input, 2-6 to 2-7
