Station Control Modules
68P81096E32-E
5
08/06/07
Host
μ
P Clock Generation
The Host
μ
P operates at a 20.4 MHz rate, generated internally from a reference
clock. A high-stability VCO in the Station Reference circuitry generates the sta-
tion master clock (16.8 MHz) which is divided by 14 (in the DSP ASIC) to
1.2 MHz and routed to the EXTAL pin of the Host
μ
P. The Host
μ
P multiplies
this reference (under software control) by 17 to produce an internal system clock
of 20.4 MHz.
Address Decoding
Host
μ
P read and write operations are performed using the Host Address and Data
buses in conjunction with four programmable chip select lines from the internal
MC68356 chip select generators, CS0 to CS3, which are used in the following
manner.
•
CS0 is used to control access to the Flash (EPROM) memory space. Since
the Flash device stores station control software, CS0 is also enabled after a
reset to access the boot ROM upon system start-up.
•
CS1, CS2 are used to control access of up to two SRAM devices.
•
CS3 is used to control access to the Parallel I/O circuitry (control signals and
SPI bus chip selects for station modules and external options).
Serial I/O Circuitry
The Serial I/O circuitry interfaces with two of the Serial Communications Inter-
face (SCI) ports (SCC1 and SCC2) on the Host
μ
P to provide general-purpose se-
rial communications buses, as follows:
•
SCC1 – this port is buffered to provide a high-speed Interprocessor Commu-
nications Bus, allowing the Host
μ
P to communicate with optional modules
(via the backplane)
•
SCC2 – serves as a serial RSS port. An 8-pin Telco connector is provided
on the front of the SCM to allow service personnel to connect a PC loaded
with the Radio Service Software (RSS) to the station, and perform program-
ming and maintenance tasks. EIA-232 Bus Receivers/Drivers interface the
connector to the SCC2 port.
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