CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
MOTOROLA
DSP56305 User’s Manual
14-13
Together, CSFTA and CSFTB form the Step Function Table as shown in Table .
14.4.3.4
Input Enable bits (INE[3:0])—CSFTB Bits 19–16
The Input Enable bits (INE[3:0]) are used to enable data input into CFS[D:A] respectively
during the input phase. When the INEx bit is cleared, data input to CFSRz is disabled for
the input phase. When the INEx bit is set, data input to CFSRz is enabled for the input
phase. Table 14-3 lists the bit numbers and their corresponding registers.
Figure 14-7
Step Function Table B Register (CSFTB)
Table 14-2
Step Function Table
Word
Address
Data Bits
Bit Location
0
WRDA[3:0]
CSFTA 3–0
1
WRDB[3:0]
CSFTA 7–4
2
WRDC[3:0]
CSFTA 11–8
3
WRDD[3:0]
CSFTA 15–12
4
WRDE[3:0]
CSFTA 19–16
5
WRDF[3:0]
CSFTA 23–20
6
WRDG[3:0]
CSFTB 3–0
7
WRDH[3:0]
CSFTB 7–4
11
10
9
8
7
6
5
4
3
2
1
0
WRDH3 WRDH2 WRDH1 WRDH0WRDG3WRDG2WRDG1WRDG0
23
22
21
20
19
18
17
16
15
14
13
12
OUTE3 OUTE2 OUTE1 OUTE0
INE3
INE2
INE1
INE0
Reserved bit, Read as zero, should be written with zero for future compatibility
AA1306
Содержание DSP56305
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