6-88
DSP56305 User’s Manual
MOTOROLA
HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.12
Interrupt Line - Interrupt Signal Configuration Register (CILP)
The CILP is a PCI standard 32-bit read-only register mapped into the PCI configuration
space, when in the PCI mode or in mode 0 (HM
=
$1 or $0). CILP is accessed if a
configuration read command is in progress and the PCI address is $FC. The CILP
register cannot be accessed by the DSP56300 core.
ML7-ML0: MAX_LAT is used for specifying how often the device needs to gain access to
the PCI bus. As the HI32 has no major requirements for the settings of Latency Timers,
these bits are hardwired to zero.
MG7-MG0: MIN_GNT is used for specifying how long a burst the device needs. As the
HI32 has no major requirements for the settings of Latency Timers, these bits are
hardwired to zero.
IP7-IP0: The Interrupt Signal bits specify which interrupt the device uses. A value of 1
corresponds to PCI INTA.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ML7
ML6
ML5
ML4
ML3
ML2
ML1
ML0
MG7
MG6
MG5
MG4
MG3
MG2
MG1
MG0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
IL7
IL6
IL5
IL4
IL3
IL2
IL1
IL0
Hardwired to zero
Hardwired to one
Bit
Name
Value
(hardwired)
Interrupt Line
7-0
IL7-IL0
---
Interrupt Signal
15-8
IP7-IP0
$01
MIN_GNT
23-16
MG7-MG0
$00
MAX_LAT
31-24
ML7-ML0
$00
Содержание DSP56305
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Страница 146: ...5 2 DSP56305 User s Manual MOTOROLA General Purpose I O 5 1 Introduction 5 3 5 2 Programming Model 5 3 ...
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