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DSP56305 User’s Manual
MOTOROLA
Core Configuration
Operating Mode Register (OMR)
4.7
OPERATING MODE REGISTER (OMR)
The Operating Mode Register (OMR) is a 24-bit read/write register divided into three
byte-sized units. The first two bytes (COM and EOM) are used to control the chip’s
operating mode. The third byte (SCS) is used to control and monitor the stack extension.
The OMR control bits are shown in Figure 4-3. Refer to the DSP56300 Family Manual for
a description of the OMR.
4.7.1
Address Tracing Enable (ATE)—OMR Bit 15
The Address Tracing Enable bit (ATE) is used to enable the Address Tracing mode,
which allows the core to reflect the addresses of internal fetches and program space
moves to the Address bus, providing assistance in software development.
11010
CCOP Cipher Processing Done (CIDN=1)
11011
Reserved
11100
Host Slave Receive Data (SRRQ=1)
11101
Host Master Receive Data (MRRQ=1)
11110
Host Slave Transmit Data (STRQ=1)
11111
Host Master Transmit Data (MTRQ=1)
DMA Request Source Bits
DRS4...DRS0
Requesting Device
Содержание DSP56305
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