12-4
DSP56305 User’s Manual
MOTOROLA
Filter Co-Processor
Features
12.2
FEATURES
• Fully programmable complex FIR filter with 16-bit resolution
• Operates concurrently with the core processor and requires minimal CPU
intervention
• Independent internal 84
×
16-bit data memory bank and 42
×
16-bit coefficient
memory bank
• Four modes of operation with optimized performance
– Mode 0—Real FIR machine with up to 42 real taps
– Mode 1—Complex FIR machine with up to 21 complex taps
– Mode 2—Complex FIR machine generating pure real and imaginary outputs
alternately. In GSM, used for performing match filtering
– Mode 3—Complex correlation of a complex data sequence with a pure real
and imaginary sequence. In GSM, used for performing cross correlation
between the received training sequence and a pre-defined mid-amble
• Two options for filter output decimation available in each operation mode,
without loss of performance
– No decimation
– Decimation by 2
• I/O data transfers via core or DMA for minimal core involvement
• Four-word deep input data buffer (24-bit word) for maximal performance
12.3
BLOCK DESCRIPTION
The FCOP comprises the following main functional blocks: PMB Interface — includes
the Data Input Buffer, Coefficients Input Buffer, Output Buffer, and Filter Counter
(FCNT)—, FCOP Data Memory Bank (FDM), FCOP Coefficients Memory Bank (FCM),
FCOP MAC machine (FMAC), Address Generator, and Control Logic.
The block diagram is presented in Figure 12-1.
Содержание DSP56305
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