6-68
DSP56305 User’s Manual
MOTOROLA
HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.2
HI32 Status Register (HSTR)
The HSTR is a 32-bit read-only status register used by the host processor to examine the
status and flags of the HI32.
When the HSTR is read to the PCI bus (HM
=
$1), the HAD31-HAD0 signals are driven
with the HSTR data during a read access.
In a 24-bit data Universal Bus mode (HM
=
$2 or $3 and HRF = $0), the HD23-HD0 signals
are driven with the three least significant HSTR bytes during a read access.
In a 16-bit data Universal Bus mode (HM
=
$2 or $3 and HRF
≠
$0), the HD15-HD0 signals
are driven with the two least significant bytes of the HSTR in a read access.
In PCI mode (HM = $1) memory space transactions, the HSTR is accessed if the PCI
address is HI32_base_address: $014.
When in a Universal Bus mode (HM
=
$2 or $3), the HSTR is accessed if the HA10-HA3
value matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0
value is $5.
The status bits are described in the following paragraphs.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HREQ
HINT
HF5
HF4
HF3
HRRQ HTRQ TRDY
Reserved, read as zero and should be written zero
Bit
Name
Function
0
TRDY
Transmitter Ready
1
HTRQ
Host Transmit Data Request
1
HRRQ
Host Receive Data Request
3-5
HF5-HF3
Host Flags
6
HINT
Host Interrupt A
7
HREQ
Host Request
31-8
reserved
Содержание DSP56305
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