...........continued
Value
Description
0x03
910 MHz
0x04
912 MHz
0x05
914 MHz
0x06
916 MHz
0x07
918 MHz
0x08
920 MHz
0x09
922 MHz
0x0A
924 MHz
Reserved
All other values are reserved
7.6.3
PLL Settling Time and Frequency Agility
When the PLL is enabled during state transition from TRX_OFF to PLL_ON or RX_ON, the settling time is typically
t
TR4
= 170 µs, including PLL self calibration. A lock of the PLL is indicated with an interrupt IRQ_0 (PLL_LOCK).
Switching between channels within a frequency band in PLL_ON or RX_ON states is typically done within t
PLL_SW
=
11 µs. This makes the radio transceiver highly suitable for frequency hopping applications.
The PLL frequency in PLL_ON and receive states is 1 MHz below the PLL frequency in transmit states. When
starting the transmit procedure, the PLL frequency is changed to the transmit frequency within a period of t
RX_TX
=
16 µs before really starting the transmission. After the transmission, the PLL settles back to the receive frequency
within a period of t
TX_RX
= 32 µs. This frequency step does not generate an interrupt IRQ_0 (PLL_LOCK) or IRQ_1
(PLL_UNLOCK) within these periods.
7.6.4
Calibration Loops
Due to variation of temperature, supply voltage and part-to-part variations of the radio transceiver the VCO
characteristics may vary.
To ensure a stable operation, two automated control loops are implemented:
• Center Frequency (CF) tuning
• Delay Cell (DCU) calibration
Both calibration loops are initiated automatically when the PLL is enabled during state transition from TRX_OFF
to PLL_ON or RX_ON state. Additionally, both calibration loops are initiated when the PLL changes to a different
frequency setting.
If the PLL operates for a long time on the same channel, for example more than five minutes, or the operating
temperature changes significantly, it is recommended to initiate the calibration loops manually.
Both calibration loops can be initiated manually by an SPI command. To start the calibration, it is recommended that
the device be in the PLL_ON state. The center frequency calibration can be initiated by setting the PLL_CF_START
bit in the PLL_CF register to ‘
1
’ (PLL_CF.PLL_CF_START =
1
). The calibration loop is completed when the IRQ_0
(PLL_LOCK) occurs, if enabled. The duration of the center frequency calibration loop depends on the difference
between the current CF value and the final CF value. During the calibration, the CF value is incremented or
decremented. Each step takes t
PLL_CF
= 8 µs. The minimum time is 8 µs; the maximum time is 270 µs. The
recommended procedure to start the center frequency calibration is to read the register 0x1A (PLL_CF), to set the
PLL_CF_START register bit to ‘
1
’ and to write the value back to the register.
The delay cell calibration can be initiated by setting the PLL_DCU_START bit in the PLL_DCU register
(PLL_DCU.PLL_DCU_START) to ‘
1
’. The delay time of the programmable delay unit is adjusted to the correct value.
The calibration works as successive approximation and is independent of the values in the PLL_DCU register. The
duration of the calibration is t
PLL_DCU
= 10 µs.
ATSAMR30M18A
Module Description
©
2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS70005384B-page 28
