For the High Data Rate Modes, the link quality value does not contain useful information; therefore, discarding it is
recommended.
7.2
Receiver (RX)
7.2.1
Overview
The AT86RF212B transceiver is split into an analog radio front-end and a digital domain. Referring to the receiver
part of the analog domain, the differential RF signal is amplified by a low noise amplifier (LNA) and split into
quadrature signals by a poly-phase filter (PPF). Two mixer circuits convert the quadrature signal down to an
intermediate frequency. Channel selectivity is achieved by an integrated band-pass filter (BPF). The subsequent
analog-to-digital converter (ADC) samples the receive signal and additionally generates a digital RSSI signal. The
ADC output is then further processed by the digital baseband receiver (RX BBP), which is part of the digital domain.
The BBP performs further filtering and signal processing. In RX_ON state, the receiver searches for the
synchronization header. Once the synchronization is established and the SFD is found, the received signal
is demodulated and provided to the Frame Buffer. Upon synchronization the receiver performs a state
change from RX_ON to BUSY_RX, which is indicated by the TRX_STATUS bits in the TRX_STATUS register
(TRX_STATUS.TRX_STATUS). Once the frame is received, the receiver switches back to RX_ON in the listen mode
on the selected channel. A similar scheme applies to the Extended Operating Mode.
The receiver is designed to handle reference oscillator accuracies up to ±60ppm; refer to the f
SRD
parameter in the
General RF Specifications
section. This results in the estimation and correction of frequency and symbol rate errors
up to ±120 ppm.
Several status information are generated during the receive process: LQI, ED and RX_STATUS. They are
automatically appended during Frame Read Access. Some information is also available through register access,
for example the PHY_ED_LEVEL.ED_LEVEL and FCS correctness with the PHY_RSSI.RX_CRC_VALID.
The Extended Operating Mode of the AT86RF212B supports frame filtering and pending data indication.
7.2.2
Frame Receive Procedure
The frame receive procedure, including the radio transceiver setup for reception and reading PSDU data from the
Frame Buffer, is described in the
Frame Receive Procedure
section.
7.2.3
Configuration
In Basic Operating Mode, the receiver is enabled by writing command RX_ON to the TRX_CMD bits in the
TRX_STATE register (TRX_STATE.TRX_CMD) in states TRX_OFF or PLL_ON. In Extended Operating Mode, the
receiver is enabled for RX_AACK operation from state PLL_ON by writing the command RX_AACK_ON.
There is no additional configuration required to receive IEEE 802.15.4 compliant frames in Basic Operating Mode.
However, the frame reception in the AT86RF212B Extended Operating Mode requires further register configurations.
For specific applications, the receiver can additionaly be configured to handle critical environment to simplify the
interaction with the microcontroller, or to operate in different data rates.
There are scenarios where CSMA-CA is not used before a transmission or where CSMA-CA is not really reliable, for
example in hidden node scenarios. As two transceivers compete for the use of one channel they may interfere with
each other which may produce unreliable transmission. Receiver Override can be used to cope with such scenarios.
The level of interference (which can be caused by a new incoming frame) is continuously measured while decoding
a frame. The synchronization to the potential new frame starts if the interference level does not allow for a reliable
detection.
The AT86RF212B receiver has an outstanding sensitivity performance. At certain environmental conditions or for
High Data Rate Modes it may be useful to manually decrease this sensitivity. This is achieved by adjusting
the synchronization header detector threshold using register the RX_PDT_LEVEL bits in the RX_SYN register
(RX_SYN.RX_PDT_LEVEL). Received signals with a RSSI value below the threshold do not activate the
demodulation process.
Furthermore, at times it may be useful to protect a received frame against overwriting by a new subsequent data
frame, when the receive data buffer has not been read on time. A Dynamic Frame Buffer Protection is enabled with
ATSAMR30M18A
Module Description
©
2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS70005384B-page 20
