Figure 7-5. Simplified XOSC Schematic with External Components
CX
CX
16MHz
XTAL2
XTAL1
EVDD
C
TRIM
C
TRIM
C
PCB
C
PCB
PCB
XTAL_TRIM[3:0]
EVDD
V
DD
XTAL_TRIM[3:0]
ATSAMR30E18A
Additional internal trimming capacitors C
TRIM
are available. Any value in the range from 0 pF to 4.5 pF with a 0.3
pF resolution is selectable using the XTAL_TRIM bits in the XOSC_CTRL register (XOSC_CTRL.XTAL_TRIM). To
calculate the total load capacitance, the following formula can be used:
C
L
[pF] = 0.5 x (CX[pF] + C
TRIM
[pF] + C
PAR
[pF]).
The ATSAMR30E18A trimming capacitors provide the possibility of reducing frequency deviations caused by
production process variations or by external components’ tolerances. Note that the oscillation frequency can only
be reduced by increasing the trimming capacitance. The frequency deviation caused by one step of C
TRIM
decreases
with increasing crystal load capacitor values.
An amplitude control circuit is included to ensure stable operation under different operating conditions and for
different crystal types. Enabling the crystal oscillator in P_ON state and after leaving SLEEP state causes a slightly
higher current during the amplitude build-up phase to ensure a short start-up time. At stable operation, the current is
reduced to the amount necessary for a robust operation. This also keeps the drive level of the crystal low.
The XTAL_TRIM value is determined during the production test and stored in NVM user row. This value needs to be
loaded into the register during initialization. For more details, see
7.5.3
Clock Jitter
The ATSAMR30M18A provides receiver sensitivities up to -105 dBm. Detection of such small RF signals requires
very clean scenarios with respect to noise and interference. Harmonics of digital signals may degrade the
performance if they interfere with the wanted RF signal. A small clock jitter of digital signals can spread harmonics
over a wider frequency range, thus reducing the power of certain spectral lines. The ATSAMR30M18A provides such
a clock jitter as an optional feature. The jitter module is working for the receiver part and all I/O signals, for example
CLKM if enabled. The transmitter part and RF frequency generation are not influenced.
7.6
Frequency Synthesizer (PLL)
The main PLL features are:
• Generate RX/TX frequencies for all supported channels
• Autonomous calibration loops for stable operation within the operating range
• Two PLL interrupts for status indication
• Fast PLL settling to support frequency hopping
7.6.1
Overview
The PLL generates the RF frequencies for the ATSAMR30M18A. During receive and transmit operations, the
frequency synthesizer operates as a local oscillator. The frequency synthesizer is implemented as a fractional-N
PLL with analog compensation of the fractional phase error. The Voltage Controlled Oscillator (VCO) is running at
double the RF frequency.
Two calibration loops ensure correct PLL functionality within the specified operating limits.
ATSAMR30M18A
Module Description
©
2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS70005384B-page 26
