58
Chapter 7: I/O Wiring
1
2
3
4
5
6
Note: Limit Switches
Normally Closed
+V
GND
GND
GND
HOME
NEG
HOME
E-STOP
NEG LIMIT
GND
POS
POS LIMIT
+24 VOLT
OPTO INPUT
LOGIC +
LOGIC -
OPTO 22
G4PB24
Logic Inputs
can be connected
to the STC -26
(m otor axes)
To:
DSPpro-VME
OPTO
OPTO
OPTO
Figure 7-5. Sample Wiring Diagram for Axis 0 Limit Switch - Opto-Isolated
Fail-safe limit operation is provided for both the optically isolated and non-isolated limit circuits.
If a wire breaks in the limit circuit the associated limit is activated and the motion is stopped
until the problem is corrected. Since the controller can be configured for either active high or
active low inputs, other limit and home sensor circuits can be used.
7.5 Dedicated and user output wiring
User outputs on the DSPpro-VME are driven by an Intel 82C55 Programmable Peripheral
Interface Controller. When power is supplied to the 82C55 these outputs have three possible
output states: High Impedance (High-Z) (1 micro amp leakage current), High ( >3.0V at 2.5
milliamp source current) , and Low ( < 0.4V at 2.5 milliamperes sink current). If there is no
power to the 82C55 the output state is held low by input protection diodes.
The figure below shows the power on and power off timing of the board output states.
Approximately .3 to .5 seconds after power is supplied to the computer the User outputs will go
to the Power-On state. This state can be any one of the three output states of the 82C55. The
Power-On state is configured at the factory to be the Low state.
Power On
Power Off
<.1 sec
.3-.5 sec
Low
Low
High - Z
High - Z
User Defined
Figure 7-6. Power On/Off Timing
Critical control signals such as amplifier enable/disable which must always be in a defined state
should be designed so that the default state of the 82C55 output is Low. A pull-down resistor
should be used to insure that the output does not float high when the output is in the High-Z state.
The following figure shows the correct wiring for amplifiers with Low Enable and High Enable
inputs:
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