LSI L64777, Техническое руководство

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Contents ix
2.17 Byte to Symbol Conversion 2-25
2.18 Differential Encoder and QAM Mapping 2-26
2.19 Pulse Shaper Structure 2-27
2.20 Output Scaling by Arithmetic Shift Right 2-29
2.21 Square-Root Raised Cosine Filter 2-34
2.22 NCO Loop Diagram 2-36
2.23 Frequency Acquisition Loop Overview 2-38
2.24 Serial Bus Base Address 2-40
3.1 Analog I/Q Output Interface Diagram 3-4
3.2 I And Q DAC Filter Diagrams 3-5
5.1 Logic Symbol for the L64777 5-2
6.1 TS Input Timing 6-3
6.2 L64777 RESET Timing Diagram 6-3
6.3 L64777 Bus 3-state Delay Timing 6-4
6.4 Package 120-Pin PQFP Pinout 6-10
6.5 120-Pin PQFP (PE) Mechanical Drawing 6-11
A.1 Quick Overview of the Serial Bus A-2
A.2 Serial Bus Write/Read Cycle A-3
A.3 General Call Structure A-4
A.4 Burst Write to Slave (Master-Transmitter, Slave-Receiver) A-5
A.5 Single Read from Slave A-7
B.1 CATV Block Diagram B-1
B.2 Signals between the L64724 and L64777 B-3
Tables
2.1 Allocation of Coefficient-Bits for Phase 0 2-30
2.2 Default Nyquist Filter Coefficients 2-32
4.1 Group 2 Bit Allocation 4-2
4.2 Reset Values for Register Fields 4-17
6.1 L64777 Absolute Maximum Ratings 6-2
6.2 L64777 Recommended Operating Conditions 6-2
6.3 L64777 DC Characteristics 6-2
6.4 L64777 Preliminary Timing Parameters 6-4
6.5 L64777 Pin Description Summary 6-5
6.6 L64777 Numerical Pin List 6-8
6.7 L64777 Alphabetical Pin List 6-9
B.1 Typical Settings of CNT_I and CNT_O B-2