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LGE Internal Use Only
Copyright © 01 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
Figure 3.2.2 Second (Main) Part of the Startup State Machine in the VPMU Domain
ͽͶ͑ͺΟΥΖΣΟΒΝ͑ΆΤΖ͑ΟΝΪ
Y\VX[^
ON key event or
RTC alarm or
charger detect or
rst connect
VPMU prepare
release reset_pmufsm_n_o
power reagion setting
SM1 ready
release reset_pmufsm_n_o
wait for system o
wait
SM1 goto SYSOFF
set reset_pmufsm_n_o
switch o PMU power region
LPMU to ULPM
sm1_goto_syso
reset_pmufsm_n_o
go to state
PMU SM1 SYSOFF
HPBG on
start HPBG in fast settie mode
default trim value
LPMU low power mode
wait for HPBG timer (~ms)
System SHUTDOWN
reset_pmu_n=0
all LDOs o (not LRTC, LPMU)
HPBG o DCXO o
Check Battery
enble battery periodic
supervision
switch HPBG to active mode
> SYSONLEV or VBAT >
SYSONPRE if prechare
LCORE, SD1 startup
LDO, SD1 startup sequence
wait for timer (~400μs)
bit ALL OFF
DCXO startup
rf_sysclk_en
System ON
reset_pmu_n=1
wait for DCXO timer (16ms)
main dig
ital sta
te machine of P
MU
small dig
ital sta
te machine in ultr
a lo
w
po
w
er LP
MU domain