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Copyright © 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
7. CIRCUIT DIAGRAM
R308
51
20
3
R
K0
1
R309
51
R310
51
R311
51
R312
51
R313
51
30
3
R
K0
1
40
3
R
K0
1
50
3
R
K0
1
60
3
R
K0
1
C318
33p
C323
33p
C320
33p
33p
C317
C316
33p
33p
C315
10
3
D
Z
20
3
D
Z
10
3
A
V
20
3
A
V
40
3
A
V
50
3
A
V
71
3
R
K7.
4
0.1u
C321
C304
33p
33p
C305
S301
5000-12P-2_95D-A1-R0
EAG63211701
C7
41
C1_1
51
C1
31
C3_1
C6
C2
C5
C5_1
C2_1
C3
C7_1
C6_1
61
6
D
N
G
VPP2
I/O2
CLK1
RST2
GND2
GND1
RST1
VPP1
CLK2
3
D
N
G
VCC1
5
D
N
G
VCC2
4
D
N
G
I/O1
K0
01
22
3
R
470
R307
C310
1u
VA308
VA309
VA312
VA311
VA310
C301
4.7u
TP301
TP302
81
3
R
K7.
4
TP303
TP304
TP305
2V85_VSIM
2V85_VSIM
FSA2259UMX
U302
EUSY0186504
6
5
7
4
8
3
9
2
10
1
C
C
V
2B1
1
B1
2A
1A
S2
S1
0
B2
1B0
D
N
G
2V85_VSIM
R325
100K
0
62
3
R
VDD_IO_1V8
VMMC_2V85
100K
R324
R301
470K
2V85_VSIM
60
3
A
V
2V85_VSIM
0.1u
C319
CN301
14
13
12
11
10
8
7
6
5
4
3
2
1
9
SW1
SW2
C322
1u
31
3
A
V
R321
10K
DNI
C311
I
N
D
41
3
R
10K
R323
2V85_VSIM
I
N
D
72
3
R
C302
0.1u
C303
0.1u
C312
0.1u
C313
0.1u
0.1u
C314
C306
4.7u
C309
0.1u
C308
0.1u
0.1u
C307
VDD_IO_1V8
VDD_IO_1V8
VDD_IO_1V8
91
3
R
K0
1
VDD_IO_1V8
U301
EAN61927501
H9DA2GH1GHMMMR-46M
B6
B3
B4
A4
A7
A3
A6
M8
L7
M7
N5
N4
M4
N3
N2
L8
M6
L6
N7
L5
M3
M2
M1
H7
D5
H8
D7
J1
G2
F2
H2
D3
F8
G8
B7
B8
C7
C8
C6
D8
C5
E6
J5
J7
K8
J8
K7
K6
K5
K4
J2
H3
E1
E2
J3
C4
D2
C3
D1
C2
B2
K3
K2
K1
J4
N9
N6
M10
L9
L2
K10
J10
H9
H1
G9
F10
E9
D10
C9
B10
B5
B1
A9
M5
A5
L4
L3
J6
H6
H5
H4
G7
G6
G5
G4
G3
F7
F6
F5
F4
F3
F1
E8
E7
E5
E4
E3
D6
D4
A2
M9
L10
K9
J9
H10
F9
E10
D9
C10
B9
N8
L1
G10
G1
C1
A8
0
1
N
1
N
0
1
A
1
A
1
C
N
6
2
C
N
8
2
C
N
9
2
C
N
VDD1
VDD2
VDD3
VDD5
VDD4
VDD6
VDDQ1
VDDQ6
VDDQ5
VDDQ4
VDDQ10
VDDQ9
VDDQ2
VDDQ8
VDDQ7
VDDQ3
NC27
NC20
NC21
NC9
NC19
NC8
NC11
NC12
NC17
NC18
NC7
NC16
NC25
NC6
NC10
NC5
NC13
NC14
NC4
NC2
NC24
NC22
NC23
A13
NC3
VCC1
VCC2
VSS1
VSS4
VSS8
VSSQ5
VSSQ4
VSSQ9
VSSQ8
VSSQ3
VSS2
VSS3
VSSQ10
VSSQ1
VSSQ2
VSS5
VSSQ6
VSSQ7
VSS6
VSS7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CK
CK
CKE
/CS
/RAS
/CAS
/WED
UDQM
LDQM
UDQS
LDQS
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
/CE
/RE
/WE
CLE
ALE
/WP
R/B
SIM_DATA
SIM_CLK
SIM_CLK
MSD_CLK
MSD_DET_N
MSD_D[1]
MSD_D[0]
MSD_CMD
MSD_D[3]
MSD_D[2]
DDR_CAS_N
DDR_RAS_N
DDR_DQS[1]
DDR_DQS[0]
DDR_DQM[0]
DDR_DQM[1]
NAND_BSY_N
NAND_CS_N
DDR_D[15]
DDR_D[05]
DDR_D[01]
DDR_D[02]
DDR_D[00]
DDR_D[14]
DDR_D[13]
DDR_D[12]
DDR_D[11]
DDR_D[10]
DDR_D[09]
DDR_D[08]
DDR_D[07]
DDR_D[06]
DDR_D[04]
DDR_D[03]
SIM_RST_SEL
SIM_SEL
NAND_DDR_WE_N
NAND_DDR_WE_N
NANDD_DDRA[00]
NANDD_DDRA[00]
NANDD_DDRA[01]
NANDD_DDRA[01]
NANDD_DDRA[10]
NANDD_DDRA[10]
NANDD_DDRA[11]
NANDD_DDRA[11]
NANDD_DDRA[12]
NANDD_DDRA[12]
NANDD_DDRA[13]
NANDD_DDRA[13]
NANDD_DDRA[14]
NANDD_DDRA[14]
NANDD_DDRA[15]
NANDD_DDRA[15]
NANDD_DDRA[02]
NANDD_DDRA[02]
NANDD_DDRA[03]
NANDD_DDRA[03]
NANDD_DDRA[04]
NANDD_DDRA[04]
NANDD_DDRA[05]
NANDD_DDRA[05]
NANDD_DDRA[06]
NANDD_DDRA[06]
NANDD_DDRA[07]
NANDD_DDRA[07]
NANDD_DDRA[08]
NANDD_DDRA[08]
NANDD_DDRA[09]
NANDD_DDRA[09]
DDR_CLK_P
NAND_WP_N
DDR_CKE
NAND_ALE_N
NAND_RE_N
NAND_CLE_N
DDR_CLK_N
DDR_CS_N
SIM_DATA_1
SIM_DATA_1
SIM_RST_N
SIM_DATA_2
SIM_DATA_2
SIM_RST_2
SIM_RST_2
DAT1
SIM Switch
SIM_CONNECTOR Dual
T8
DAT0
Micro_SD
8-3-1-2_Push_168T_Ver1.0
T5
T4
T3
If Dual SIM, R327=DNI and U302=Insert.
T2
T1
If single SIM, R327=0ohm and U302=DNI.
Pin Number
MCP2-1_2G_1G DDRx16_hynix
VSS
CLK
VDD
CMD
CD/DAT3
DAT2
Description
T7
MSD_DET_N
T6
High
Low
Insert
No card