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Specifying Clock/Reset and External Ports
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LatticeMico32 Hardware Developer User Guide
Clock port – The clock signal is provided by the WISHBONE interconnect
through the GUI-generated wrapper as an input to your component’s clock
port. All WISHBONE transactions are synchronized to this clock signal.
This port is required.
Reset port – The reset signal is provided by the WISHBONE interconnect
through the GUI-generated wrapper as an input to your component’s reset
port. This port is required.
Interrupt port – If your component needs to issue interrupts for the
processor to handle, you can specify this output port from your component
as an interrupt signal to the processor routed through the GUI-generated
wrapper. You cannot specify multiple interrupt ports; that is, your
component cannot have more than one interrupt signal to the processor.
This port is optional.
External input/output ports – If your component has input or output ports
that must be made available as platform input and output signals (usually
for connection to logic external to the platform or for board connection),
you can specify these ports in the External Ports tab. This port is optional.
As an example, consider the port definition of a custom component that must
be made available in MSB:
In this example, the custom component has four external signals that must be
made available as platform inputs and outputs. It also requires an interrupt
line to be connected to the processor. The component’s mandatory clock
input port is named “wb_clk,” and the mandatory reset port is named “wb_rst.”
Figure 32: Port Definition of a Custom Component
module MyVerilogComponent (
// wishbone interface
input [31:0] wb_slv_addr,
input [31:0] wb_slv_master_data,
input wb_slv_cyc,
input wb_slv_stb,
input [3:0] wb_slv_sel,
input wb_slv_we,
output [31:0] wb_slv_slave_data,
output wb_slv_ack,
output wb_slv_err,
output wb_slv_rty,
// mandatory clock/reset signals
input wb_clk,
input wb_rst,
// external interface (optional)
output [15:0] external_out_bus,
input [8:0] external_in_bus,
input external_in_wire,
output external_out_wire,
// interrupt signal to the processor(s)
output interrupt_signal
)
