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Performing HDL Functional Simulation of LatticeMico32 Platforms
40
LatticeMico32 Hardware Developer User Guide
Performing HDL Functional Simulation of
LatticeMico32 Platforms
In most cases, the platforms that are created using the LatticeMico System
Builder work correctly in hardware because the existing components have
been tested many times. New custom components, however, start as
untested elements and will probably need debugging through HDL functional
simulation.
This topic describes the process for using an HDL simulation tool such as
Mentor Graphics ModelSim™ or Aldec Active-HDL™. The method described
is applicable to designs written in VHDL, Verilog, or a combination of both.
The example LatticeMico32 platform in this topic uses the FPGA's on-chip
memory, Embedded Block Ram (EBR). The firmware (C/C++ code) is
compiled using the Lattice C/C++ SPE and Debug software, and a memory
initialization file is created that is loaded into the on-chip memory. It is possible
to locate the firmware in other off-chip memories as long as there exists a
behavioral model for the memory.
The example application used in this topic is the “Hello World” application,
which is available as a predefined C/C++ SPE project. See Chapter 2 and
Chapter 6 of the
LatticeMico System Software Developer User Guide
for more
information about creating the “Hello World” application, compiling it, and
deploying it to the EBR.
The platform in Figure 16 shows a Verilog design (platform) that is
instantiated from within a VHDL module.The platform is an instantiation of
Platform C with the following additional components:
EBR – At least one EBR is required to hold the software/firmware.
Figure 17 on page 41 shows the design’s EBR component setup, along
Figure 16: Platform Setup
