Lattice Semiconductor LatticeMico32, Руководство пользователя для разработчиков аппаратного обеспечения

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U
SING THE
L
ATTICE
M
ICO
S
YSTEM
S
OFTWARE
: Performing HDL Functional Simulation of LatticeMico32 Platforms
LatticeMico32 Hardware Developer User Guide
43
Figure 19: VHDL Wrapper
library ieee;
use IEEE.std_logic_1164.all;
entity Platform_vhd is
port (
clk_i : in std_logic;
reset_n : in std_logic;
sramsram_wen : out std_logic;
sramsram_data : inout std_logic_vector(31 downto 0);
sramsram_addr : out std_logic_vector(22 downto 0);
sramsram_csn : out std_logic;
sramsram_be : out std_logic_vector(3 downto 0);
sramsram_oen : out std_logic;
LEDPIO_OUT : out std_logic_vector(7 downto 0);
uartSIN : in std_logic;
uartSOUT : out std_logic;
);
end Platform_vhd;
architecture structural of Platform_vhd is
component Platform
port (
clk_i : in std_logic;
reset_n : in std_logic;
sramsram_wen : out std_logic;
sramsram_data : inout std_logic_vector(31 downto 0);
sramsram_addr : out std_logic_vector(22 downto 0);
sramsram_csn : out std_logic;
sramsram_be : out std_logic_vector(3 downto 0);
sramsram_oen : out std_logic;
LEDPIO_OUT : out std_logic_vector(7 downto 0);
uartSIN : in std_logic;
uartSOUT : out std_logic;
);
end component;
begin
Platform_u : Platform
port map (
clk_i => clk_i,
reset_n => reset_n,
sramsram_wen => sramsram_wen,
sramsram_data => sramsram_data,
sramsram_addr => sramsram_addr,
sramsram_csn => sramsram_csn,
sramsram_be => sramsram_be,
sramsram_oen => sramsram_oen,
LEDPIO_OUT => LEDPIO_OUT,
uartSIN => uartSIN,
uartSOUT => uartSOUT,
);
end structural;