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Creating the Microprocessor Platform in MSB

36

LatticeMico32 Hardware Developer User Guide

<

platform_name

>/components/i2cm_opencores/rtl/verilog

See the 

Synthesis Data Flow Tutorial

 for step-by-step information about 

synthesizing designs in Precision RTL Synthesis and Synplify Pro.

To create an EDIF file:

1. Start the synthesis tool.

2. Create a new project in the tool. 

3. Add the Verilog HDL file output by MSB to the project.

4. Set the target device and the options. 

5. Compile the project and specify the timing objectives.

6. Synthesize the design to generate an EDIF (.edn or .edf) file.

Design Guidance for Platform 
Performance

Setting preferences and performing static timing analysis can help achieve 
higher platform design performance or minimize area utilization. The following 
documents give instructions and examples for setting design constraints:

Achieving Timing Closure in FPGA Designs

 – This tutorial provides 

techniques for optimizing design performance and demonstrates the 
influence of map and place-and-route preferences. It uses a system-on-
chip design that utilizes an OpenRISC 1200 processor and Wishbone on-
chip bus.

FPGA Design Guide

 – The chapter "Strategies for Timing Closure" gives 

instructions for constraining your design, performing static timing analysis, 
and floorplanning.

Additionally, see the following sections of the Diamond online Help 

Constraints Reference Guide – This section provides syntax and 
descriptions for all preferences

Applying Design Constraints – This section consists of guidelines for 
setting preferences

Generating the Microprocessor 
Bitstream

For Windows, you now return to Diamond to import the platform source files. 
You import the Verilog file output by MSB; or for mixed Verilog/VHDL, you 
import both the Verilog and VHDL files output by MSB. For Linux, you import 
the EDIF file output by the synthesis tool. You also specify the connections 
from the microprocessor to the chip pins by importing an .lpf file. You can 
optionally perform functional simulation and timing simulation. Primarily, you 

Содержание LatticeMico32

Страница 1: ...LatticeMico32 Hardware Developer User Guide May 2014...

Страница 2: ...rademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and or other countries ISP Bringing the Best Together and More of the Best are service marks of Lattice Semicond...

Страница 3: ...commands code syntax and path names Ctrl L Press the two keys at the same time Courier Code examples Messages reports and prompts from the software Omitted material in a line of code Omitted lines in...

Страница 4: ...iv LatticeMico32 Hardware Developer User Guide...

Страница 5: ...Microprocessor Platform in MSB 15 Starting MSB 15 Creating a Platform Description in MSB 17 Connecting Master and Slave Ports 21 Changing Master Port Arbitration Priorities 26 Assigning Component Add...

Страница 6: ...ing Clock Reset and External Ports 61 Specifying RTL Files 72 Specifying User Configurable Parameters 74 RTL Parameters 75 RTL Parameter Value Types 75 Predefined RTL Parameters 76 Software Parameters...

Страница 7: ...ures of your embedded soft core microprocessor The LatticeMico System is composed of three bundled applications Mico System Builder MSB C C Software Project Environment C C SPE Debugger These applicat...

Страница 8: ...ective are also available in the Debug perspective because the functions are so intertwined Figure 1 shows the interaction of the three LatticeMico System applications with Lattice Diamond in the micr...

Страница 9: ...develop drivers as necessary for available peripherals and add them to the platform you created 4 In the MSB perspective generate a platform build which automatically creates a build structure with as...

Страница 10: ...y new application development or modification to the platform in step 2 Figure 2 shows the LatticeMico System design flow For complete information about using the C C SPE and Debugger perspectives to...

Страница 11: ...he C C Development Toolkit CDT in the Eclipse Workbench LatticeMico Asynchronous SRAM Controller which describes the features and functionality of the LatticeMico asynchronous SRAM controller LatticeM...

Страница 12: ...otes on LatticeEC and LatticeECP devices LatticeECP EC Family Data Sheet LatticeECP2 FPGA Family Handbook which is a collection of the data sheets and application notes on LatticeECP2 devices LatticeE...

Страница 13: ...tomized the user interface LatticeMico System Software Overview This section provides a brief synopsis of the functional tools included in the software and teaches you the basic concept of user perspe...

Страница 14: ...Mico System s system requirements on the Red Hat Linux operating system see the Installing LatticeMico32 Development Tools chapter of the Diamond release_number Installation Notice for Linux available...

Страница 15: ...by default After working in the interface the software defaults to the last opened perspective The Eclipse workbench that is integrated into the LatticeMico System software has three activation button...

Страница 16: ...existing default perspectives in LatticeMico System by changing the existing set of commands ascribed to each perspective To customize an existing perspective 1 From within a given perspective choose...

Страница 17: ...ives that you defined yourself but you cannot delete the default perspectives that are delivered with the software workbench environment To delete a custom perspective 1 From within a given perspectiv...

Страница 18: ...In each perspective views are defined for each perspective that allow you to interactively perform a task These views are described later in this chapter for each perspective At times you may want to...

Страница 19: ...and line run the following script Diamond_install_path bin ispgui 2 Choose File New Project 3 In the New Project wizard click Next 4 Type a name for the project in the Name box 5 Click the Browse butt...

Страница 20: ...ew Platform Wizard opens In the Directory text box it displays the path and directory of your Diamond project 3 Give the new platform a name and specify the settings as described in Creating a Platfor...

Страница 21: ...ster and slave ports assign addresses and interrupt priorities and generate the platform Creating the Microprocessor Platform in MSB After you have created a new project in Diamond using your target F...

Страница 22: ...w which displays all the available components that you can use to create the design List of hardware components microprocessors memories peripherals and bus interfaces Bus interfaces can be masters or...

Страница 23: ...rocessor It is not applicable to memories Disable which excludes a component from a platform definition It can be toggled on and off Component Help view which displays information about the component...

Страница 24: ...SB perspective choose File New Platform The New Platform Wizard dialog box now appears as shown in Figure 6 2 In the New Platform Wizard dialog box enter the name of the platform in the Platform Name...

Страница 25: ...n msb file This file will hold the contents of your platform a CPU its peripherals and the interconnections between them Currently the platform description contains no components You will add componen...

Страница 26: ...20 for instructions To add a peripheral component to the design 1 Double click on the component in the Available Components view set any options in the dialog box that appears and click OK 2 After you...

Страница 27: ...s one or more slave ports or both Arbitration Schemes The connections that MSB makes depend on which arbitration scheme you choose while creating the platform Shared Bus Arbitration MSB automatically...

Страница 28: ...slave ports as long as they do not try to access the same slave at the same time Each master port connected to the arbiter has priority of access to the slave ports In the case of simultaneous access...

Страница 29: ...ccess to the bus in a round robin fashion Both the slave side fixed and the slave side round robin arbitration schemes use separate arbiters for each multi master slave so the area of the platforms ge...

Страница 30: ...a desired connection to master instruction data ports or both You may or may not wish to connect to both master ports depending on the necessary input on a given slave component For example suppose t...

Страница 31: ...d enabled in the MSB perspective after all components have been added in a slave side fixed arbitration scheme Figure 12 shows the Platform Tools menu with the Edit Arbitration Priorities command disa...

Страница 32: ...d arbitration schemes This option is disabled for the slave side round robin arbitration scheme since it is not applicable To change master port arbitration priorities 1 In the MSB perspective click i...

Страница 33: ...s would be 0 1 and 2 If you defined more than three values for any master an error message would appear as shown for the UART slave example in Figure 13 Assigning Component Addresses After you add you...

Страница 34: ...base addresses of individual components so that MSB will not assign them new addresses See Locking Component Addresses on page 29 for details Automatically Assigning Component Addresses Initially you...

Страница 35: ...session 2 Choose File Save The locked address is now saved in the msb file Manually Editing Component Addresses You can manually assign an address to an individual component after automatically assign...

Страница 36: ...b file Performing Design Rule Checks You can ensure that your design conforms to the design rules for a given device by performing a design rule check DRC To perform a design rule check and verify the...

Страница 37: ...tab or anywhere inside the view You can also right click and choose Run Generator from the pop up menu If you edit the msb file after it has been generated save it by choosing File Save As An asterisk...

Страница 38: ...Create VHDL Wrapper option in the New Platform Wizard dialog box It is intended to be used only to incorporate the Verilog based platform into a VHDL design The platform_name _vhd vhd file contains t...

Страница 39: ...e following assign sramflashDATA sramsram_wen sramsram_data_out flashsram_wen flashsram_data_out 32 bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ If you want to change that connection you must manually modify the...

Страница 40: ...le and the VHDL wrapper file is used to connect to the other VHDL user logic No I O pad is inserted in the ngo file except these bidirectional signals To avoid double buffering these bidirectional por...

Страница 41: ...Precision RTL Synthesis as your synthesis tool 1 Add the platform_name v file into your Precision RTL project 2 Add the following directory paths into your Precision RTL search path platform_name soc...

Страница 42: ...tutorial provides techniques for optimizing design performance and demonstrates the influence of map and place and route preferences It uses a system on chip design that utilizes an OpenRISC 1200 proc...

Страница 43: ...ox browse to the platform_name soc location and do one of the following Select the platform_name v file Verilog and click Add If your design is mixed Verilog VHDL select both the platform_name v file...

Страница 44: ...n constraint assignments see the Applying Design Constraints and Constraints Reference Guide in the Lattice Diamond online Help You can import the pin constraints specified for a template platform int...

Страница 45: ...ent USB cable select HW USBN 2A Lattice HW USBN 2A USB port programming cable or HW USBN 2B FTDI Lattice HW USBN 2B FTDI USB programming cable in the Cable Type box and change the connection port in t...

Страница 46: ...on chip memory Embedded Block Ram EBR The firmware C C code is compiled using the Lattice C C SPE and Debug software and a memory initialization file is created that is loaded into the on chip memory...

Страница 47: ...ations through any HDL simulator The following steps are required Ensure that the LM32 Exception Base Address EBA points to the base address of the memory component that contains the deployed software...

Страница 48: ...LM32 processor dialog box platform v This file contains the top level module of the design which is Platform in this example pmi_def v This file contains module definitions of all the PMI modules use...

Страница 49: ...ic uartSOUT out std_logic end Platform_vhd architecture structural of Platform_vhd is component Platform port clk_i in std_logic reset_n in std_logic sramsram_wen out std_logic sramsram_data inout std...

Страница 50: ...ench A testbench is required to functionally verify a design The example testbench shown in Figure 20 on page 44 instantiates Platform_vhdl the top level module of the design Figure 20 Testbench File...

Страница 51: ...l_m scall_w always negedge clk_i begin if Platform_u Platform_u LM32 cpu stall_m 1 b0 begin scall_m Platform_u Platform_u LM32 cpu scall_x Platform_u Platform_u LM32 cpu valid_x scall_w scall_m Platfo...

Страница 52: ...are located in the simulation directory of the Diamond installation diamond_install_path cae_library simulation verilog pmi Select the behavioral model of each PMI module from the simulation directory...

Страница 53: ...SING THE LATTICEMICO SYSTEM SOFTWARE Performing HDL Functional Simulation of LatticeMico32 Platforms LatticeMico32 Hardware Developer User Guide 47 Figure 22 PMI Models in Platform Simulation Director...

Страница 54: ...ule in the design The list shown is not intended to be complete for all possible LM32 designs vlog define SIMULATION soc platform v acom soc platform_vhd vhd vlog incdir Components lm32_top rtl verilo...

Страница 55: ...g working directory For the ECP2 the behavioral code is located at isptools cae_library simulation verilog ecp2 vsim work testbench t 1ps novopt L ecp2_vlg Using LatticeMico System as a Stand Alone To...

Страница 56: ...am 4 Sends all software developers the Mico System Builder project directory For example 5 Sends the software developers the FPGA bitstream file bit that was generated using Diamond Software Developer...

Страница 57: ...shows an HDL diagrammatic representation of your custom component This chapter assumes that you have implemented your custom component and that your custom component has a WISHBONE interface that cont...

Страница 58: ...e parameters that your RTL design software or both may need if applicable 7 Optionally specify software elements 8 Specify the optional software files that your custom component may provide for use in...

Страница 59: ...Import Create Custom Component dialog box It enables you to specify attributes for your custom component It also provides the location for creating the custom component and the MSB specific component...

Страница 60: ...ucture shown in Figure 26 This directory structure is created in the directory specified in the New Component Directory box This directory structure is created only after all the information is provid...

Страница 61: ...Browse button to browse to your new component folder Note Your new component folder should be outside of the micosystem folder Select Component XML Specifies the path of the component description file...

Страница 62: ...d Stores elf file rodata boot and text sections in memory Write Stores elf file bss and data sections in memory Read Write Stores any elf section in memory HTML Help Specifies the name of the help fil...

Страница 63: ...in order for entries to be visible in the Master Slave Ports group box You can update an existing master or slave port connection by clicking on the appropriate row in the spreadsheet view Make any c...

Страница 64: ...pecifies a prefix that is used for two purposes It creates a unique name for the component ports connected to the WISHBONE bus for example prefix _DAT_O It enables you to use the same instance name fo...

Страница 65: ...ed in a platform The component icon displays a small red x in the bottom left hand corner If you are going to overwrite an existing component another message appears that asks permission to overwrite...

Страница 66: ...ons 1 From the drop down menu in the Type box of the Master Slave Ports tab select SlavePort as shown in Figure 29 2 In the Display Name box type slave so that MSB will display this port s name as sla...

Страница 67: ...alog box This tab continues the task of building a Verilog wrapper around the custom component You use this tab to define the CLK_I RST_I and optional INTR_O control signals The component port specifi...

Страница 68: ...NTS IN LATTICEMICO SYSTEM Specifying Clock Reset and External Ports 62 LatticeMico32 Hardware Developer User Guide Figure 29 Selecting the Slave Port Step 1 Select SlavePort Step 2 Specify display nam...

Страница 69: ...MPONENTS IN LATTICEMICO SYSTEM Specifying Clock Reset and External Ports LatticeMico32 Hardware Developer User Guide 63 Figure 30 Entering the Signal Names Step 4 Specify component port signals Step 5...

Страница 70: ...ernal Ports Tab Note You cannot create dynamic width input and output ports by using the Import Create Custom Component dialog box You must directly edit the XML to create these ports Table 5 External...

Страница 71: ...e wrapper port named in the Component Port field Update Updates the port parameters list Whenever a change is made to the Port Attribute entries that you wish to make permanent you must click the Upda...

Страница 72: ...t ports that must be made available as platform input and output signals usually for connection to logic external to the platform or for board connection you can specify these ports in the External Po...

Страница 73: ...specify the clock reset and external port connections 1 Select the Clock Port line in the External Ports tab as shown in Figure 33 2 Enter wb_clk in the Connect To box as shown in Figure 34 3 Click t...

Страница 74: ...hen the selected interrupt port s signal value is high Active low means that your component asserts an interrupt when the selected interrupt port s signal value is low The MSB platform generator inser...

Страница 75: ...ion to the component s external_out_bus port as shown in Figure 37 3 Since this is an output port from the component select the Direction pull down menu and select output 4 Since the external port is...

Страница 76: ...CREATING CUSTOM COMPONENTS IN LATTICEMICO SYSTEM Specifying Clock Reset and External Ports 70 LatticeMico32 Hardware Developer User Guide Figure 36 Specifying the Interrupt Port Connection...

Страница 77: ...tion for the other port specifications Modify the editable boxes and select the Add button to add the other port specifications Once you have done this the External Ports tab should look like Figure 3...

Страница 78: ...ly acceptable HDL type is Verilog and the files must have a v extension You specify the Verilog HDL files in the RTL Files tab of the Import Create Custom Component dialog box Figure 39 provides an ov...

Страница 79: ...onent and specify the name of the Verilog black box module The GUI creates a wrapper that instantiates the top level module of the Verilog custom component or the Verilog black box module for a VHDL c...

Страница 80: ...nt not when you create a new custom component Delete Use this button to delete files from the Import RTL Files list Highlight the file that you wish to remove from the list and click Delete Directory...

Страница 81: ...ameter Value Types The parameters specified in the Parameters tab are made available to you for configuration through a component configuration dialog box in MSB You enter or select the parameter s va...

Страница 82: ...ponent in a platform Address Lock Specifies the default value for lock as used in MSB You can change this value when you instantiate the component in a platform Disable Specifies the default value for...

Страница 83: ...Developer User Guide for more information on the file support implementation for LatticeMico32 GUI Presentation The MSB perspective displays a configuration dialog box for your custom component when y...

Страница 84: ...equency Although the Import Create Custom Component dialog box enables you to specify a widget MSB overrides and automatically assigns a value to the parameter declared as a Frequency type Figure 40 S...

Страница 85: ...et is spinner or combo Step 9 Click Add button Table 10 Parameters Tab Options Option Description Parameter Name Specifies the name of the parameter to be passed to the Verilog source code When using...

Страница 86: ...iler flag specifies that this is a compiler option to be used in C C SPE Complier Options If compiler flag is selected specify flag or option Standard I O This option is only available for CharIODevic...

Страница 87: ...n presented in the Software tab The format of the C structure generated in DDStructs h is shown in Figure 42 You can additionally specify elements of the structure to be initialized with the values co...

Страница 88: ...ments Step 1 Enter function name Step 2 Enter structure name Step 3 Add structure members a Select a data type or enter a data type name c Select box if an array b Enter member name d Select parameter...

Страница 89: ...on function If your component needs to know the interrupt line it is connected to in a platform you can add an int or an unsigned int data member and declare its value as Interrupt C C SPE automatical...

Страница 90: ...e DDStruct Attributes group box Reset Clears the DDStruct Attributes group box controls DRC Performs a design rule check of the new component Save Adds the custom component to LatticeMico32 If the des...

Страница 91: ...latform library build process and becoming part of the platform library archive Platform library file type These source files are compiled during the platform library build process and become part of...

Страница 92: ...iles if an existing custom component is being edited Table 14 lists the options available in the Software Files tab of the Import Create Custom Component dialog box Table 14 Software Files Tab Options...

Страница 93: ...wrapper 1 Create a component definition in VHDL that is LatticeMico32 compliant for example using WISHBONE Refer to the section WISHBONE Interconnect Architecture in the LatticeMico32 Processor Refer...

Страница 94: ...the Verilog wrapper has no visibility into the VHDL ngo black box element preventing any reconciliation of multiple tristate buffers The black box pad declaration directs the synthesis process not to...

Страница 95: ...relative path For example an absolute path might be c ispTOOLS version examples VHDL_Test LM32_Platform soc A relative path would be a path relative to the Diamond project directory For example if th...

Страница 96: ...he automatically generated Verilog wrapper instantiates your custom component allowing MSB to connect the custom component to the rest of the platform Saving the Settings All the settings specified in...

Страница 97: ...he service files must be implemented to support the LatticeMico32 initialization process Each component must define a basic set of service functions that have been defined by the LatticeMico32 boot pr...

Страница 98: ...demonstrates how to Make the created component available in MSB Provide a component customization dialog box for configuring RTL instantiation parameters Add software support files and generate instan...

Страница 99: ...k WISHBONE interface signals below This component does not support burst transfers wb_adr Address from master wb_master_data Data from master wb_cyc WISHBONE cycle valid qualifier wb_stb WISHBONE tran...

Страница 100: ...general purpose reg_04 read only 32 bit register that contains the WISHBONE platform clock frequency MHz reg_08 read only register that contains a constant specified when instantiating this component...

Страница 101: ...sign read_data reg_00_sel 1 b1 reg_00 reg_04_sel 1 b1 reg_04 reg_08_sel 1 b1 reg_08_int_val 32 hdeadbeef assign write ack registered always posedge wb_clk or posedge wb_reset if wb_reset begin write_a...

Страница 102: ...egin reg_04 CLK_MHZ_INT_VALUE end else begin if reg_04_sel 1 b1 wb_we 1 b1 write_ack 1 b0 begin if wb_sel 0 1 b1 begin reg_04 7 0 wb_master_data 7 0 end if wb_sel 1 1 b1 begin reg_04 15 8 wb_master_da...

Страница 103: ...alization function void init_reg_device struct st_reg_device ctx simply copy initialization data for reg_08 provided in the context structure to register 00 REG_DEV_REGISTER ctx b_addr 0 ctx reg_08_va...

Страница 104: ...The Verilog source code for this component is shown in Verilog RTL Implementation on page 92 Table 15 lists the input and output signals for the example component Figure 50 Component s Port Diagram Ta...

Страница 105: ...s Output 8 External pins contains value of the lowest byte of reg_00 Table 15 Input Output Signals in the Example Custom Component Table 16 Registers in the Example Custom Component Byte Offset Regist...

Страница 106: ...cture contains a member b_addr that corresponds to the component s base address which is assigned by MSB It also contains a member reg_08_value which must contain the 32 bit value used for initializin...

Страница 107: ...on as shown in Figure 53 to open the Import Create Custom Component graphical user interface 2 Enter the component information as shown in Figure 54 Figure 52 Source Directory Figure 53 Opening the Im...

Страница 108: ...as shown in Figure 57 6 Optionally specify the component s interrupt signal information as shown in Figure 58 If your component does not have an interrupt line you do not need to perform this step Si...

Страница 109: ...CREATING CUSTOM COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example LatticeMico32 Hardware Developer User Guide 103 Figure 55 Specifying the WISHBONE Slave Port Signals for the Component...

Страница 110: ...CREATING CUSTOM COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example 104 LatticeMico32 Hardware Developer User Guide Figure 56 Specifying the WISHBONE Clock Signal for the Component...

Страница 111: ...CREATING CUSTOM COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example LatticeMico32 Hardware Developer User Guide 105 Figure 57 Specifying the WISHBONE Reset Signal for the Component...

Страница 112: ...CREATING CUSTOM COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example 106 LatticeMico32 Hardware Developer User Guide Figure 58 Specifying the Interrupt Signal for the Component...

Страница 113: ...CREATING CUSTOM COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example LatticeMico32 Hardware Developer User Guide 107 Figure 59 Specifying the External Port for the Component...

Страница 114: ...Developer User Guide Figure 61 shows the steps required for adding a GUI widget for configuring the reg_08 register s value when you instantiate the custom component in a platform Figure 60 Specifyin...

Страница 115: ...CREATING CUSTOM COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example LatticeMico32 Hardware Developer User Guide 109 Figure 61 Adding a Configuration Widget for the reg_08 Register...

Страница 116: ...ough you can change it when you instantiate it in the platform it is always a good idea to make sure that the default value is sufficient to cover the entire addressable space for example the space fo...

Страница 117: ...member that should contain the component s base address parameter BASE_ADDRESS as shown in Figure 65 Add name as a const char member that should contain the component s name parameter InstanceName Th...

Страница 118: ...e 69 so that you can configure it when instantiating it in a platform Figure 70 shows the directory structure and the contents of the directories created by the MSB graphical user interface The direct...

Страница 119: ...CREATING CUSTOM COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example LatticeMico32 Hardware Developer User Guide 113 Figure 66 Adding the C Source File...

Страница 120: ...COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example 114 LatticeMico32 Hardware Developer User Guide Figure 67 Adding the Device Driver Header h File Figure 68 Custom Component in MSB Available...

Страница 121: ...STOM COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example LatticeMico32 Hardware Developer User Guide 115 Figure 69 Add Reg_Comp Dialog Box Figure 70 Directories Created by the MSB Graphical User...

Страница 122: ...CREATING CUSTOM COMPONENTS IN LATTICEMICO SYSTEM Custom Component Example 116 LatticeMico32 Hardware Developer User Guide...

Страница 123: ...ser source object files that have been compiled and assembled from their source C files breakpoints Breakpoints are a combination of signal states that are used to indicate when simulation should stop...

Страница 124: ...s an abbreviation for C C development tools which are components or plug ins of the Eclipse development environment on which the LatticeMico System is based default linker script The default linker sc...

Страница 125: ...files contain scripts that define what files the make utility must use to compile and link during the build process There are many makefiles employed in the LatticeMico System build process The makefi...

Страница 126: ...t files platform library object o file The platform library object o file is a compiled output of the library source files and is input for creating platform library archive files platform settings fi...

Страница 127: ...everything in a workspace folder Basically a workspace represents everything you do in the LatticeMico System software what is available how you view it and what options are available to you through...

Страница 128: ...GLOSSARY 122 LatticeMico32 Hardware Developer User Guide...

Страница 129: ...ents view 16 20 B behavioral model 46 bidirectional data buses 33 bidirectional ports 34 bitstream generating in Diamond 37 38 black_box_pad_pin attribute 88 Board Frequency parameter 19 breakpoints d...

Страница 130: ...flow 14 Diamond Installation Notice document 6 Directory parameter 18 DMA controller see LatticeMico DMA controller document icon 20 double buffered bidirectional ports 34 DRC 21 27 30 E Eclipse 118...

Страница 131: ...ling 19 perspectives 9 running on Linux 13 15 running on Windows 8 system requirements on Linux 8 system requirements on Windows 8 using 7 LatticeMico timer available in MSB perspective 20 LatticeMico...

Страница 132: ...to 19 adding processor to 19 assigning component addresses 27 assigning interrupt request priorities 30 changing master port arbitration priorities 26 connecting master and slave ports 21 24 creating...

Страница 133: ...ver transmitter see LatticeMico UART V v files 31 33 Verilog msb file used in flow 31 v file used in flow 31 adding logic to enable bidirectional bus sharing 33 creating platform in 31 creating top le...

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