Lattice Semiconductor LatticeMico32, Руководство пользователя для разработчиков аппаратного обеспечения

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: Specifying WISHBONE Interface Connections
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LatticeMico32 Hardware Developer User Guide
The example in Figure 28 shows the steps required for specifying a slave port
connection on the custom component. Consider the following module
definition for a custom component:
In this module definition, there are three sets of signals: slave WISHBONE
port signals, mandatory clock/reset signals, and external interface signals
specific to the component’s behavior. In the Master/Slave Ports tab, only the
slave WISHBONE port signals are added. The mandatory clock/reset and the
external interface signals are added in the next tab.
To specify the master and slave port connections:
1. From the drop-down menu in the Type box of the Master/Slave Ports tab,
select SlavePort , as shown in Figure 29.
2. In the Display Name box, type slave so that MSB will display this port’s
name as “slave” beneath the component’s instance name.
3. In the Prefix box, enter S . The prefix is only used internally within MSB.
4. Enter the component’s corresponding signal names, as shown in
Figure 30.
5. Click Add to add the port specification for the component.
Table 4: LatticeMico32 Slave Component WISHBONE Ports
Component Port Names for
WISHBONE Slave Port Direction Width Required
<Prefix >_ADR_I Input 32 Yes
<Prefix >_DAT_I Input 32 No
< Prefix >_WE_I Input 1 Yes
< Prefix >_SEL_I Input 4 Yes
< Prefix >_STB_I Input 1 Yes
< Prefix >_CYC_I Input 1 Yes
< Prefix >_LOCK_I Input 1 No
< Prefix >_CTI_I Input 3 ‘No
< Prefix >_BTE_I Input 2 No
< Prefix >_DAT_O Output 32 No
< Prefix >_ACK_O Output 1 Yes
< Prefix >_ERR_O Output 1 No
< Prefix >_RTY_O Output 1 No