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Creating the Microprocessor Platform in MSB
34
LatticeMico32 Hardware Developer User Guide
from the platform and you are using the VHDL wrapper, then you must also
modify the <
platform_name
>_vhd.vhd file in the ./<
platform_name
>/soc
directory.
However, if you regenerate the platform in MSB after you add logic to the
tristates, these additions will be lost in the automatically generated
<
platform_name
>.v or <
platform_name
>_vhd.vhd file in the
./<
platform_name
>/soc directory. To avoid losing your work, copy the modified
<
platform_name
>.v or <
platform_name
>_vhd.vhd file to another location,
regenerate the platform, and then copy the modified <
platform_name
>.v or
<
platform_name
>_vhd.vhd file back to the ./<
platform_name
>/soc directory.
Connecting Bidirectional Ports of a Platform
Tristates can only be connected to external ports.
Avoiding Double-Buffered Bidirectional Ports in
VHDL NGO Flow
In the flow for VHDL users who have selected the optional “Create VHDL
NGO File,” the platform resides in an .ngo file, and the VHDL wrapper file is
used to connect to the other VHDL user logic. No I/O pad is inserted in the
.ngo file except these bidirectional signals. To avoid double-buffering these
bidirectional ports, you must declare them as black-box pads. This declaration
tells the synthesis tool that a black-box port has an I/O buffer already
implemented inside the black box and therefore the synthesis tool should not
put another I/O buffer for this port in the netlist that it is creating. Here is an
example:
component platform_xxx
port(
D: in std_logic;
E: in std_logic;
GINOUT : inout std_logic_vector(2 downto 0);
Q : out std_logic
);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of platform_xxx: component is true;
attribute black_box_pad_pin : string;
attribute black_box_pad_pin of platform_xxx: component is
"GINOUT(2:0)";
When you declare the I/O ports as black-box pads during VHDL synthesis, the
synthesis tools do not insert I/O pads for these signals and therefore avoid
double buffering.
Figure 15 further clarifies the connection. For all non-bidirectional I/Os, the I/O
buffers (in green) are provided by the VHDL wrapper during VHDL synthesis.
The bidirectional I/O buffers (in red) are provided by the .ngo file itself.
