Lattice Semiconductor LatticeMico32/DSP, Руководство пользователя

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34
LatticeMico32/DSP Development Board
Lattice Semiconductor User’s Guide
Appendix A. Schematics
Figure 12.
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
SE
G
_
C
A
0
#
SEG_A# SEG_B# SE
G
_
C
#
SE
G
_
D
#
SEG_E# SE
G
_
F
#
SE
G
_
D
P
#
DS
W
0
DS
W
1
DS
W
2
DS
W
3
SE
G
_
C
A
1
#
SEG_G#
T
S
T
_
STEP
TST_COL0 TST_COL2 TST_COL1
LE
D
7
#
LE
D
0
#
LE
D
1
#
LE
D
2
#
LE
D
3
#
LE
D
5
#
LE
D
6
#
TST_ROW0 TST_ROW3 TST_ROW2 TST_ROW1 LC
D
_
R
E
G
S
E
L
LC
D
_
R
W
LC
D
_
E
N
A
B
L
E
R
S
_C
TS_LVTTL
R
S
_R
X
D
_LVTTL
RS_TXD_LVTTL R
S
_R
TS_LVTTL
USB_
GPI
O
[2
8
:0
]
USB_
P
W
E
N
0
USB
_
O
C
0
#
USB_
P
W
E
N
1
USB
_
O
C
1
#
USB_
P
W
E
N
2
USB
_
O
C
2
#
CARDSE
L
#
CODEC_
SC
L
K
CODEC_
D
IN
CODEC_
CS#
CODEC_
BC
L
K
CODEC_
L
R
C
IN
CODEC_
D
O
U
T
CODEC
_
M
C
L
K
CODEC_
L
R
CO
U
T
CODEC
_
S
D
IN
VGA_
R
D
0
VGA_
R
D
1
VG
A
_
G
R
0
VGA_BL0
VG
A
_
G
R
1
VGA_
H
S
Y
N
C
VGA_BL1 V
G
A_VSY
N
C
LE
D
4
#
ETH_TXER ETH_TXD3 ETH_TXD1 ETH_TXD0 ETH_TXEN ETH_TXCLK
E
T
H_R
XER
ETH_
RX
D
3
ETH_
RX
D
2
ETH_
RX
D
0
ETH_
RX
C
L
K
ETH_RXDV ETH_
C
R
S
ET
H
_
C
O
L
ETH_
RX
D
1
ETH_TXD2
ETH_M
DC
ET
H
_
M
D
IO
ETH
_
M
D
IN
T
R
#
H
P
E_RESOUT#
C
L
K
_FPGA
EX
PCON
_
C
L
K
IN
EX
PCON_CLKOUT
I2
C
_
S
C
L
1
I2
C
_
S
D
A
1
DAC_
D
IG
DAC_
A
N
A
L
O
G
FLASH_
C
E
#
SRAM
_CE#
ME
MORY
_
O
E
#
ME
M
O
R
Y
_
W
E
#
FLASH_W
P
#/
A
C
C
ME
MORY
_
A
[2
2
:0
]
ME
MORY
_
D
Q
[3
1
:0
]
FLASH_B
Y
T
E
#
FLASH_RY
/B
Y
#
_
A
FLASH_RY
/B
Y
#
_
B
SR
AM
_BE0#
SR
AM
_BE1#
SR
AM
_BE2#
SR
AM
_BE3#
F
L
ASH_RESET#
HPE_RESET# EX
PCON_I
O
[4
5
:0
]
U
SB_M
ISO
USB_
S
S
I#
USB_
S
C
K
U
SB_M
O
SI
USB_TXD D
D
R_CKE0
DD
R
_
B
A
0
DD
R
_
W
E
#
D
D
R_RAS#
D
D
R_CAS#
DD
R
_
S
0
#
D
D
R
_
D
Q
[3
1:
0]
DDR_
A
[1
3
:0
]
DDR_
C
K0
+
D
D
R_
CK0
-
D
D
R
_
D
Q
S[
3:
0]
DDR
_
D
M
[3
:0
]
DDR_
C
K1
+
CODE
C
_
M
O
D
E
US
B
_
R
X
D
US
B
_
R
T
S
US
B
_
C
T
S
MA
CH
X
O
_
IO
[6
:0
]
M
A
C
H
X
O
_CLK0
DD
R
_
C
K
E
1
DDR_
V
R
E
F
DD
R
_
S
1
#
DD
R
_
B
A
1
D
D
R_
CK1
-
HSC
O
N
_
D
A
T
1
+
H
S
C
O
N_DAT1-
HSC
O
N
_
D
A
T
2
+
HSCO
N
_
D
A
T
2
-
HSC
O
N
_
D
A
T
0
+
H
S
C
O
N_DAT0-
HSC
O
N
_
D
A
T
3
+
HSCO
N
_
D
A
T
3
-
HSCO
N
_
D
A
T
0
-
H
S
C
O
N_DAT0
+
H
S
C
O
N_DAT1
+
H
S
C
O
N
_
D
A
T1-
H
S_D
AT1-
H
S
_D
AT0-
HSCO
N
_
D
A
T
3
-
HSCO
N
_
D
A
T
2
-
H
S
C
O
N_DAT2
+
H
S
C
O
N_DAT3
+
H
S
_D
AT2-
CL
K
_
F
P
G
A
VGA_
R
D
0
VGA_
R
D
1
VG
A
_
G
R
0
VGA_BL0 VG
A
_
G
R
1
VGA_
H
S
Y
N
C
VGA_BL1 V
G
A_VSY
N
C
USB_
G
P
IO
0
USB_
G
P
IO
1
USB_
G
P
IO
2
USB_
G
P
IO
3
USB_
G
P
IO
4
USB_
G
P
IO
5
USB_
G
P
IO
6
USB_
G
P
IO
7
USB_
G
P
IO
8
USB_
G
P
IO
9
USB
_
G
P
IO
1
0
USB
_
G
P
IO
1
1
USB
_
G
P
IO
1
2
USB
_
G
P
IO
1
3
USB
_
G
P
IO
1
4
USB
_
G
P
IO
1
5
USB
_
G
P
IO
1
6
USB
_
G
P
IO
1
7
USB
_
G
P
IO
1
8
USB
_
G
P
IO
1
9
USB
_
G
P
IO
2
0
USB
_
G
P
IO
2
1
USB
_
G
P
IO
2
2
USB
_
G
P
IO
2
3
USB
_
G
P
IO
2
4
USB
_
G
P
IO
2
5
USB
_
G
P
IO
2
6
USB
_
G
P
IO
2
7
USB
_
G
P
IO
2
8
ME
M
O
R
Y
_
D
Q
5
ME
M
O
R
Y
_
D
Q
6
ME
M
O
R
Y
_
D
Q
3
ME
M
O
R
Y
_
D
Q
1
ME
M
O
R
Y
_
D
Q
2
ME
M
O
R
Y
_
D
Q
0
ME
M
O
R
Y
_
D
Q
7
ME
M
O
R
Y
_
D
Q
4
ME
M
O
R
Y
_
D
Q
9
ME
M
O
R
Y
_
D
Q
8
ME
MORY
_
A
9
ME
MORY
_
A
1
1
ME
MORY
_
A
1
0
ME
MORY
_
A
1
3
ME
MORY
_
A
1
5
ME
MORY
_
A
1
4
ME
MORY
_
A
1
2
ME
MORY
_
A
1
7
ME
MORY
_
A
1
9
ME
MORY
_
A
1
8
ME
MORY
_
A
1
6
ME
MORY
_
A
2
1
ME
MORY
_
A
2
2
ME
MORY
_
A
2
0
ME
MORY
_
A
5
ME
MORY
_
A
7
ME
MORY
_
A
6
ME
MORY
_
A
4
ME
MORY
_
A
1
ME
MORY
_
A
3
ME
MORY
_
A
2
ME
MORY
_
A
0
ME
MORY
_
A
8
ME
M
O
R
Y
_
D
Q
1
1
ME
M
O
R
Y
_
D
Q
1
0
ME
M
O
R
Y
_
D
Q
1
5
ME
M
O
R
Y
_
D
Q
1
2
ME
M
O
R
Y
_
D
Q
1
7
ME
M
O
R
Y
_
D
Q
1
9
ME
M
O
R
Y
_
D
Q
1
8
ME
M
O
R
Y
_
D
Q
1
6
ME
M
O
R
Y
_
D
Q
2
1
ME
M
O
R
Y
_
D
Q
2
3
ME
M
O
R
Y
_
D
Q
2
2
ME
M
O
R
Y
_
D
Q
2
0
ME
M
O
R
Y
_
D
Q
2
4
ME
M
O
R
Y
_
D
Q
2
6
ME
M
O
R
Y
_
D
Q
2
8
ME
M
O
R
Y
_
D
Q
2
7
ME
M
O
R
Y
_
D
Q
2
5
ME
M
O
R
Y
_
D
Q
3
0
ME
M
O
R
Y
_
D
Q
3
1
ME
M
O
R
Y
_
D
Q
2
9
ME
M
O
R
Y
_
D
Q
1
3
ME
M
O
R
Y
_
D
Q
1
4
SRAM
_CE#
SR
AM
_BE0#
SR
AM
_BE1#
ME
MORY
_
O
E
#
ME
M
O
R
Y
_
W
E
#
FLASH_
C
E
#
FLASH_W
P
#/
A
C
C
FLASH_B
Y
T
E
#
FLASH_RY
/B
Y
#
_
A
FLASH_RY
/B
Y
#
_
B
F
L
ASH_RESET#
SR
AM
_BE3#
SR
AM
_BE2#
I2
C_SDA1
I2
C
_
S
C
L
1
R
S
_C
TS_LVTTL
R
S
_R
X
D
_LVTTL
R
S
_R
TS_LVTTL
RS_TXD_LVTTL TST_ROW0 TST_ROW1 TST_ROW2 TST_ROW3
T
S
T
_
STEP
DS
W
0
DS
W
1
DS
W
2
DS
W
3
LE
D
0
#
LE
D
1
#
LE
D
2
#
LE
D
3
#
LE
D
4
#
LE
D
5
#
LE
D
6
#
LE
D
7
#
SE
G
_
C
#
SE
G
_
D
#
SEG_G# SE
G
_
D
P
#
SE
G
_
C
A
0
#
SE
G
_
C
A
1
#
LC
D
_
R
W
LC
D
_
R
E
G
S
E
L
L
C
D_
EN
A
B
L
E
TST_COL0 SEG_A# SEG_B# SEG_E# SE
G
_
F
#
TST_COL2 MACHX
O_
IO
5
M
A
C
H
X
O
_IO3
MACHX
O_
IO
4
M
A
C
H
X
O
_IO6
CL
K
_
F
P
G
A
HPE_RESET# M
A
C
H
X
O
_CLK0
M
A
C
H
X
O
_IO0
M
A
C
H
X
O
_IO1
M
A
C
H
X
O
_IO2
ETH_TXER ETH_
RX
D
V
ETH_
C
R
S
ET
H
_
C
O
L
ETH_M
D
C
ET
H
_
M
D
IO
ETH
_
M
D
IN
T
R
#
ETH_TXCLK ETH_
RX
C
L
K
ETH_TXD3 ETH_TXD1 ETH_TXEN ETH_TXD2 ETH_RX
ER
ETH_
RX
D
2
ETH_
RX
D
0
ETH_
RX
D
1
ETH_
RX
D
3
ETH_TXD0 U
SB_M
O
SI
USB_TXD USB
_
O
C
0
#
U
S
B
_
PW
EN0
U
S
B
_
PW
EN1
U
S
B
_
PW
EN2
USB
_
O
C
1
#
USB
_
O
C
2
#
D
D
R_
DQS3
DDR_
DM3
DD
R
_
A
9
DD
R
_
A
1
1
DD
R
_
A
1
2
DD
R
_
A
5
DD
R
_
A
6
DD
R
_
A
7
DD
R
_
A
8
DD
R
_
A
1
DD
R
_
A
2
DD
R
_
A
3
DD
R
_
A
4
DD
R
_
A
0
DD
R
_
A
1
3
DD
R
_
D
Q
2
8
HS_
D
AT3
+
DD
R
_
A
1
0
DD
R
_
D
Q
2
4
DD
R
_
D
Q
2
5
DD
R
_
D
Q
2
6
DD
R
_
D
Q
2
7
DD
R
_
D
Q
2
9
DD
R
_
D
Q
3
0
DD
R
_
D
Q
3
1
D
D
R_CKE1
D
D
R_CAS#
D
D
R_RAS#
DDR_
V
R
E
F
DD
R
_
B
A
0
DD
R
_
B
A
1
DD
R
_
W
E
#
DD
R
_
S
0
#
DD
R
_
S
1
#
DDR
_
D
Q
0
DDR
_
D
Q
6
DDR
_
D
Q
5
DDR_
DM0
D
D
R_
DQS0
DDR
_
D
Q
4
D
D
R_
DQS2
DDR_
D
M2
DD
R
_
D
Q
1
6
DD
R
_
D
Q
1
7
DD
R
_
D
Q
1
8
DD
R
_
D
Q
1
9
DD
R
_
D
Q
2
0
DD
R
_
D
Q
2
1
DD
R
_
D
Q
2
2
DD
R
_
D
Q
2
3
HS_
D
AT1
+
H
S
_D
AT1-
DDR_
CK0
+
DD
R
_
C
K
0
-
H
S
_D
AT0-
DDR_
CK1
+
D
D
R_
CK1
-
DDR_
V
R
E
F
D
D
R_
DQS1
DDR_
D
M1
DDR
_
D
Q
7
DDR
_
D
Q
1
DDR
_
D
Q
3
DDR
_
D
Q
2
DDR
_
D
Q
8
DDR
_
D
Q
9
DD
R
_
D
Q
1
0
DD
R
_
D
Q
1
1
DD
R
_
D
Q
1
2
DD
R
_
D
Q
1
3
DD
R
_
D
Q
1
4
DD
R
_
D
Q
1
5
D
D
R_CKE0
BB3V3_C
L
K0-
BB3V3_I
O
[1
1
:0
]
BB3
BB3V3_C
LK0-
BB3
B
B
3V3_I
O
4
B
B
3V3_I
O
5
B
B
3V3_I
O
6
B
B
3V3_I
O
7
B
B
3V3_I
O
8
B
B
3V3_I
O
9
B
B
3V3_I
O
1
0
B
B
3V3_I
O
1
1
B
B
2V5_I
O
0
B
B
2V5_I
O
1
B
B
2V5_I
O
2
B
B
2V5_I
O
3
B
B
2V5_I
O
4
B
B
2V5_I
O
5
B
B
2V5_I
O
7
H
S
_D
AT4-
B
B
2V5_I
O
6
E
X
PCON_
IO
1
E
X
PCON_
IO
3
E
X
PCON_
IO
2
E
X
PCON_
IO
0
E
X
PCON_
IO
7
E
X
PCON_
IO
1
4
E
X
PCON_
IO
4
E
X
PCON_
IO
8
E
X
PCON_
IO
9
E
X
PCON_
IO
5
E
X
PCON_
IO
2
3
E
X
PCON_
IO
2
4
E
X
PCON_
IO
2
2
E
X
PCON_
IO
2
7
E
X
PCON_
IO
2
6
E
X
PCON_
IO
2
5
E
X
PCON_
IO
3
0
E
X
PCON_
IO
2
9
E
X
PCON_
IO
2
8
E
X
PCON_
IO
3
2
E
X
PCON_
IO
3
1
E
X
PCON_
IO
3
5
E
X
PCON_
IO
3
3
E
X
PCON_
IO
3
4
E
X
PCON_
IO
1
0
E
X
PCON_
IO
1
3
E
X
PCON_
IO
1
2
E
X
PCON_
IO
6
E
X
PCON_
IO
1
5
E
X
PCON_
IO
1
1
E
X
PCON_
IO
1
8
E
X
PCON_
IO
1
6
E
X
PCON_
IO
1
9
E
X
PCON_
IO
1
7
E
X
PCON_
IO
2
0
EX
PCON
_
C
L
K
IN
EX
PCON_CLKOUT
E
X
PCON_
IO
2
1
CARDSE
L
#
E
X
PCON_
IO3
6
E
X
PCON_
IO3
7
E
X
PCON_
IO3
8
E
X
PCON_
IO4
5
DAC_
D
IG
TST_COL1
CODEC_
D
IN
CODEC
_
M
C
L
K
CODEC_
D
O
U
T
CODEC_
CS#
CODEC_
SC
L
K
CODEC_
L
R
C
IN
CODEC_
BC
L
K
CODEC
_
S
D
IN
CODEC_
L
R
CO
U
T
CODE
C
_
M
O
D
E
H
P
E_RESOUT#
U
SB_M
ISO
USB_
S
S
I#
USB_
S
C
K
US
B
_
R
X
D
US
B
_
R
T
S
US
B
_
C
T
S
BB2V5_I
O
[7
:0
]
HS_
D
AT2
+
H
S
_D
AT2-
H
S
_D
AT3-
H
S
_D
AT3-
HSCO
N
_
D
A
T
4
-
H
S
C
O
N_D
A
T
4+
HS_D
A
T
4+
H
S
_D
AT4-
HSC
O
N
_
D
A
T
4
+
H
S
C
O
N_DAT4-
GN
D
GND
_
D
A
C
GND
_
D
A
C
GN
D
GN
D
GN
D
VCC2
V
5
GN
D
VCC1
V
2
VCC3
V
3
GN
D
GN
D
VCC2
V5
VCC3
V
3
VCC2
V5
VCC3
V
3
VCC3
V3
VCC3
V
3
VCC3
V3
VCC3
V
3
GN
D
VCC3
V
3
VCC1
V
2
GN
D
DS
W
0
5
DS
W
1
5
DS
W
2
5
DS
W
3
5
TST_ROW0
5 TST_ROW1
5 TST_ROW2
5
LED
0
#
5
TST_ROW3
5
LED
2
#
5
LED
1
#
5
LED
3
#
5
LED
5
#
5
LED
4
#
5
LED
6
#
5
SE
G
_
C
A
0
#
5
LED
7
#
5
SEG_B#
5 SE
G
_
C
A
1
#
5
SEG
_
C
#
5
SEG_E#
5 SEG
_
F
#
5
SEG_G#
5 SEG_A#
5 SE
G
_
D
P
#
5
TST_COL0
5
SEG
_
D
#
5
TST_COL1
5 T
S
T
_STEP
5
TST_COL2
5 LC
D
_
R
E
G
S
E
L
5
LC
D
_
R
W
5
LC
D
_
E
N
A
B
L
E
5
R
S
_C
TS_LVTTL
7
R
S
_R
X
D
_LVTTL
7
RS_TXD_LVTTL
7 R
S
_R
TS_LVTTL
7
USB_
GPI
O
[2
8
:0
]
7
USB_PW
E
N
0
7
USB_O
C
0
#
7
USB_PW
E
N
1
7
USB_O
C
1
#
7
USB_PW
E
N
2
7
USB_O
C
2
#
7
CARDSEL
#
9
CODEC_
SCL
K
10
CODEC_
D
IN
10
CODEC_
CS#
10
CODEC_
BCL
K
10
CODEC_
L
R
C
IN
10
CODEC_
DOU
T
10
CODEC_
M
C
L
K
10
CODEC_
L
R
COU
T
10
CODEC
_
S
D
IN
10
VGA_
R
D
0
10
VGA_
R
D
1
10
VGA_GR0
10
VGA_GR1
10
VGA_BL0
10
VGA_H
S
Y
N
C
10
VGA_BL1
10
VG
A
_
V
S
Y
N
C
10
ETH_TXER
8 ETH_TXD3
8 ETH_TXD2
8 ETH_TXD1
8 ETH_TXD0
8 ETH_TXEN
8 ETH_TXCLK
8
ETH_
RX
E
R
8
ETH_
RX
D
3
8
ETH_
RX
D
2
8
ETH_
RX
D
1
8
ETH_
RX
D
0
8
ETH_
RX
C
L
K
8
ETH_RX
DV
8
ETH_
C
R
S
8
ET
H
_
C
O
L
8
ETH_
M
D
IN
T
R
#
8
ET
H
_
M
D
C
8
ET
H
_
M
D
IO
8
H
P
E_RESOUT#
6
,7,
8,
9
C
LK_F
P
G
A
6
EX
PCON_
C
L
K
IN
9
EX
PCON_CLKOUT
9
I2
C_SDA1
6
I2
C
_
S
C
L
1
6
FLASH_CE
#
4
SRAM
_CE#
4
ME
MORY
_
O
E
#
4
ME
M
O
R
Y
_
W
E
#
4
FLASH_W
P
#/
ACC
4
ME
MORY
_
A
[2
2
:0
]
4M
E
M
O
R
Y
_
D
Q
[3
1
:0
]
4
FLASH_BY
T
E
#
4
FLASH_RY/
B
Y
#
_
A
4
FLASH_RY/
B
Y
#
_
B
4
SR
AM
_BE0#
4
SR
AM
_BE1#
4
SR
AM
_BE2#
4
SR
AM
_BE3#
4
F
L
A
S
H_RESET#
4
HPE_RESET#
3,
6 EX
PCON_I
O
[4
5
:0
]
3,
9
USB_M
ISO
7
USB_S
S
I#
7
USB_
S
C
K
7
USB_M
O
SI
7
USB_TXD
7 D
D
R_
CKE0
4
DDR_
BA0
4D
D
R
_
B
A
1
4
DDR_
V
R
E
F
4
DD
R
_
W
E
#
4
D
D
R_
RAS#
4
DD
R
_
C
A
S
#
4
DD
R
_
S
0
#
4
DD
R
_
S
1
#
4
D
D
R
_
D
Q
[3
1:
0]
4
DDR_
A
[1
3
:0
]
4
DDR_
CK0
+
4
DD
R
_
C
K
0
-
4
DDR_
D
Q
S
[3
:0
]
4
D
D
R
_
DM[3
:0
]
4
D
D
R_
CK1
+
4
CODEC_
M
O
D
E
10
U
SB_RX
D
7
US
B
_
R
T
S
7
US
B
_
C
T
S
7
M
A
C
H
X
O
_
IO[6
:0
]
3M
A
C
H
X
O
_
C
L
K
0
3
D
D
R_
CKE1
4
D
D
R_
CK1
-
4
HSCO
N
_
D
A
T
1
+
9
HSCON
_
D
A
T
1
-
9
H
S
C
O
9
HSCON_
D
A
T
2
-
9
HSCO
N
_
D
A
T
0
+
9
HSCON
_
D
A
T
0
-
9
H
S
C
O
9
HSCON_
D
A
T
3
-
9
BB3V3_C
L
K0-
9
BB3V3_C
L
K0+
9
BB3V3_I
O
[1
1
:0
]
3,
9
BB2V5_I
O[
7
:0
]
9
HSCO
N
_
D
A
T
4
+
9
HSCON
_
D
A
T
4
-
9
:t
e
e
h
S
:t
c
ej
or
P Aut
h
or
s:
Re
v
is
io
n
:
Cre
a
te
d
:
Las
t m
o
d
if
ie
d
:
IF
W
:
of
Page
A
G
P
F
_
2
0
12
2
La
tt
ice LFEC33 FPGA
Of
fpage
Hum
a
n Inter
fa
c
e
RS2
3
2
USB
E
thernet
E
x
p
a
n
s
io
n
C
onnectors and Prototy
p
ing Area
Audio Codec
VG
A
Clock / Re
s
e
t
Sternpunkt an
X
1
Me
m
o
ry
DA
C
C
o
n
fi
guration
LVD
S
t
e
rm
ination
LVD
S
LVD
S
LVD
S
LVD
S
LVD
S
LVD
S
LVD
S
LVD
S
Place the 0402-resistors of
the LVDS termination
as close as possibl
e
t
o
the FPGA.
LVD
S
LVD
S
LVD
S
LVD
S
LVD
S
LVD
S
LVD
S
R0
2
0
9
0
R0
0
12
BANK 2
B
ANK 3
U
0
201B
LFECP/
E
C
3
3
-4
8
4
B
G
A
PR34B/PCLKC2_0
J22
PR34A/PCLKT2_0
J21
PR33B
H22
PR33A
H21
PR32B
L19
PR32A
L18
PR31B
K20
PR30A
K18
PR30B
K19
PR31A/RDQS31
J20
PR29B
G22
PR29A
F22
PR28B
F21
PR28A
E22
PR27B
E21
PR27A
D22
PR26B
G21
PR26A
G20
PR25B
J18
PR25A
H19
PR24B
J19
PR24A
H20
PR23B
H17
PR23A/RDQS23
H18
PR17B/RU_PLLC_FB
D21
PR17A/RU_PLLT_FB
C22
PR16B/RU_PLLC_IN
G19
PR16A/RU_PLLT_IN
G18
PR15B
F20
PR15A
F19
PR14B
E20
PR14A/RDQS14
D20
PR13B
C21
PR13A
C20
PR12B
F18
PR12A
E18
PR11B
B22
PR11A
B21
PR2B/VREF1_2
E19
PR2A/VREF2_2
D19
VREF1_3/PR68A
Y20
VREF2_3/PR68B
W20
PR59A
AB21
PR59B
AA21
PR58A
V19
PR58B
W19
RDQS57/PR57A
AA22
RL_PLLT_IN/PR56A
U20
RL_PLLC_IN/PR56B
V20
RL_PLLT_FB/PR55A
Y22
RL_PLLC_FB/PR55B
W21
PR49A
R17
PR49B
T18
RDQS48/PR48A
R18
PR47B
U22
PR46B
R21
PR45B
P20
PR44B
P19
PR43B
P21
PR42B
N21
PR41B
N19
PR40B
M21
PR39B
L21
PR38B
M18
PR37B
M22
PR36B
K22
PR48B
R19
PR47A
T22
PR46A
R22
PR45A
N20
PR44A
P18
PR43A
P22
PR42A
N22
PR41A
N18
RDQS40/PR40A
L20
PR39A
M20
PR38A
M19
PR37A
L22
PR36A
K21
R
0
213
n
b
_100R
1 2
100n C0
2
2
4
100n C
021
8
100n C0
2
1
2
R0
2
1
1
0
R0
0
12
100n C0
2
3
4
100n C0
2
3
0
R
0
204
n
b
_100R
1 2
nb_4p70 C
0
240
R0
2
1
5
0
R0
0
12
R
0
210
n
b
_100R
1 2
100n C0
2
1
3
1n00 C
022
8
100n C0
2
0
3
100n C0
2
3
1
BANK 0
B
ANK 1
U
0
201A
LFECP/
E
C
3
3
-4
8
4
B
G
A
PT33B/PCLKC0_0
A11
PT33A/PCLKT0_0
A10
PT32B/VREF1_0
E12
PT32A/VREF2_0
E11
PT31B
B11
PT31A
C11
PT30B
B9
PT30A/TDQS30
B10
PT29B
A9
PT29A
A8
PT28B
D11
PT28A
C10
PT27B
A7
PT27A
A6
PT26B
B7
PT25A
B6
PT25B
A5
PT26A
B8
PT24B
G10
PT24A
E10
PT23B
F10
PT23A
D10
PT22B
G9
PT22A/TDQS22
E9
PT21B
C9
PT21A
C8
PT20B
F9
PT20A
D9
PT19B
F8
PT19A
D7
PT18B
D8
PT18A
C7
PT17B
A4
PT17A
B4
PT16B
C4
PT16A
C5
PT15B
D6
PT15A
B5
PT14B
E6
PT14A/TDQS14
C6
PT13B
A3
PT13A
B3
PT12B
F6
PT12A
D5
PT11B
F7
PT11A
E8
PT10B
G6
PT10A
E7
PT57A
F17
PT57B
G17
PT56A
C18
PT56B
D18
PT55A
B20
PT55B
C19
TDQS54/PT54A
C16
PT54B
D17
PT53A
A20
PT53B
B19
PT52A
C17
PT52B
E17
PT51A
E16
PT51B
F16
PT50A
D16
PT50B
F15
PT49A
A19
PT49B
B18
PT48A
A18
PT48B
B17
PT47A
A17
PT47B
B16
TDQS46/PT46A
A16
PT45B
A15
PT44B
G14
PT43B
D15
PT42B
C14
PT41B
A13
PT40B
E14
PT39B
F14
PT38B
E13
PT37B
A12
PT36B
F13
VREF2_1/PT35B
F12
PT34B
F11
PT46B
B15
PT45A
A14
PT44A
E15
PT43A
C15
PT42A
B14
PT41A
B13
PT40A
C13
PT39A
D14
TDQS38/PT38A
G13
PT37A
B12
PT36A
D13
VREF1_1/PT35A
D12
PT34A
C12
R0
2
1
7
0
R0
0
12
100n C
023
5
100n C
022
7
POWER SUPP
L
Y
U0
2
0
1
F
L
F
E
C
P
/EC33-
484BG
A
GND
R8
GND
R15
GND
P9
GND
P14
GND
P13
GND
P12
GND
P11
GND
P10
GND
N9
GND
N14
GND
N13
GND
N12
GND
N11
GND
N10
GND
M9
GND
M14
GND
M13
GND
M12
GND
M11
GND
M10
GND
L9
GND
L14
GND
L13
GND
L12
GND
L11
GND
L10
GND
K9
GND
K14
GND
K13
GND
K12
GND
K11
GND
K10
GND
J9
GND
J14
GND
J13
GND
J12
GND
J11
GND
J10
GND
H8
GND
H15
GND
AB22
GND
AB1
GND
A22
GND
A1
VCC
J16
VCC
J7
VCC
K16
VCC
K17
VCC
K6
VCC
K7
VCC
L17
VCC
L6
VCC
M17
VCC
M6
VCC
N16
VCC
N17
VCC
N6
VCC
N7
VCC
P16
VCC
P7
VCCIO0
G11
VCCIO0
H10
VCCIO0
H11
VCCIO0
H9
VCCIO1
G12
VCCIO1
H12
VCCIO1
H13
VCCIO1
H14
VCCIO2
J15
VCCIO2
K15
VCCIO2
L15
VCCIO2
L16
VCCIO3
M15
VCCIO3
M16
VCCIO3
N15
VCCIO3
P15
VCCIO4
R12
VCCIO4
R13
VCCIO4
R14
VCCIO4
T12
VCCIO5
R10
VCCIO5
R11
VCCIO5
R9
VCCIO5
T11
VCCIO6
M7
VCCIO6
M8
VCCIO6
N8
VCCIO6
P8
VCCIO7
J8
VCCIO7
K8
VCCIO7
L7
VCCIO7
L8
R0
2
0
6
0
R0
0
12
100n C0
2
0
1
100n C0
2
2
5
100n C0
2
3
2
100n C
0
202
R0
2
0
8
0
R0
0
1
2
+
C
0
220
4u70
1 2
R
0
216
n
b
_100R
1 2
100n C0
2
1
4
100n C0
2
1
5
+
C
0
211
4u70
1 2
BANK 4
B
ANK 5
U0
2
0
1
C
LFECP/
E
C
3
3
-4
8
4
B
G
A
PB57B
U17
PB57A
T17
PB56B
W18
PB56A
Y18
PB55B
Y19
PB54A/BDQS54
Y16
PB54B
W17
PB55A
AA20
PB53B
AA19
PB53A
AB20
PB52B
V17
PB52A
Y17
PB51B
U16
PB51A
V16
PB50B
U15
PB50A
W16
PB49B
AA18
PB49A
AB19
PB48B
AA17
PB48A
AB18
PB47B
AA16
PB47A
AB17
PB46B
AA15
PB46A/BDQS46
AB16
PB45B
AB15
PB45A
AB14
PB44B
T14
PB44A
V15
PB43B
W15
PB43A
Y15
PB42B
Y14
PB42A
AA14
PB41A
AA13
PB40A
Y13
PB39A
W14
PB38A/BDQS38
T13
PB36A/VREF2_4
W13
PB35A/VREF1_4
W12
PB29A
AB8
PB29B
AB9
PB28A
Y10
PB28B
W11
PB27A
AB6
PB27B
AB7
PB26A
AA8
PB26B
AA7
PB25A
AA6
PB25B
AB5
PB24A
V10
PB24B
T10
PB23A
W10
PB23B
U10
BDQS22/PB22A
V9
PB21B
Y9
PB20B
U9
PB19B
U8
PB18B
W8
PB17B
AB4
PB16B
Y4
PB15B
W6
PB14B
V6
PB13B
AB3
PB12B
U6
PB11B
U7
PB10B
T6
PB22B
T9
PB21A
Y8
PB20A
W9
PB19A
W7
PB18A
Y7
PB17A
AA4
PB16A
Y5
PB15A
AA5
BDQS14/PB14A
Y6
PB13A
AA3
PB12A
W5
PB11A
V8
PB10A
V7
BDQS30/PB30A
AA10
PB30B
AA9
PB31A
Y11
PB31B
AA11
VREF2_5/PB32A
V11
VREF1_5/PB32B
V12
PCLKT5_0/PB33A
AB10
PCLKC5_0/PB33B
AB11
R0
2
1
2
0
R0
0
12
R
0
207
n
b
_100R
1 2
100n C
023
6
R0
2
0
2
33
k
2
1
2
100n C0
2
2
1
100n C
022
6
4p70 C0
2
3
9
X1 HD
R
2
1 2
100n C
021
6
R0
2
1
4
0
R0
0
12
R0
2
0
3
0
R0
0
12
R0
2
0
5
0
R0
0
12
1n00 C0
2
1
0
100n C0
2
2
2
1n00 C0
2
1
9
BANK 6
B
ANK 7
U0
2
0
1
D
LFECP/
E
C
3
3
-4
8
4
B
G
A
PL57B
Y2
PL57A/LDQS57
Y1
PL56B
W2
PL56A
W1
PL55B
V5
PL54A/LL_PLLT_FB
U3
PL54B/LL_PLLC_FB
V3
PL55A
U4
PL53B/LL_PLLC_IN
V2
PL53A/LL_PLLT_IN
V1
PL49B
T3
PL49A
R3
PL48B
T2
PL48A/LDQS48
T1
PL47B
R4
PL47A
R5
PL46B
R2
PL46A
R1
PL45B
P4
PL45A
P3
PL44B
P5
PL44A
R6
PL43B
P2
PL43A
P1
PL42B
N2
PL42A
N1
PL41B
N4
PL41A
N5
PL40B
M3
PL40A/LDQS40
N3
PL39B
M2
PL39A
M1
PL38B
M5
PL38A
M4
PL37B
L1
PL37A
L2
PL36B
L5
PL36A
L4
PCLKT7_0/PL34A
J1
PCLKC7_0/PL34B
K1
PL33A
K3
PL33B
K2
PL32A
K4
PL32B
K5
LDQS31/PL31A
J2
PL31B
H1
PL30A
J4
PL30B
J3
PL29A
H2
PL29B
G1
PL28A
H3
PL28B
G2
PL27A
E1
PL26B
F1
PL25B
H5
PL24B
H4
PL23B
H6
PL15B
D2
PL14B
G4
PL12B
C2
PL11B
F5
PL10B
B2
VREF1_7/PL2B
E4
PL27B
D1
PL26A
F2
PL25A
J5
PL24A
G3
LDQS23/PL23A
G5
LU_PLLT_IN/PL16A
B1
PL15A
E3
LDQS14/PL14A
F4
PL12A
D3
PL11A
E5
PL10A
C3
VREF2_7/PL2A
D4
LU_PLLC_IN/PL16B
C1
LU_PLLT_FB/PL17A
F3
LU_PLLC_FB/PL17B
E2
PL58A
AA1
PL58B
AA2
PL59A
W4
PL59B
V4
PL68A/VREF1_6
W3
PL68B/VREF2_6
Y3
100n C0
2
0
8
R0
2
0
1
0R
00
1 2
100n C
021
7
+
C
0
229
4u70
1 2