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LatticeMico32/DSP Development Board
Lattice Semiconductor
User’s Guide
Introduction
This document describes the features and functionality of the LatticeMico32/DSP Development Board. This board
is designed as a hardware platform for design and development with the LatticeMico32 microprocessor, as well as
for the LatticeMico8 microcontroller, and for various DSP functions.
This document describes the numerous functional elements of the board. The schematics of the board can be
found in the appendix at the end of this document.
Features
• LatticeECP™ FPGA with 33,800 LUT4s, 131 kbit of embedded RAM, 4 PLLs, and 360 user I/O pins
• Lattice MachXO™ with 640 LUTs
• Serial Flash with 8 Mbit for non-volatile storage of FPGA configuration data.
• DDR SODIMM socket for DDR SDRAM modules (DDR1, 100-133MHz, 32-bit data bus)
• Parallel Flash 2x128 Mbit, organized as 8M 32-bit words
• SRAM 2x4 Mbit, organized as 256K 32-bit words
• USB 2.0 connector and integrated ispDOWNLOAD
®
cable for programming the FPGA
• Flywire connector for programming using an ispDOWNLOAD cable (available separately)
• 9-pin RS232 serial port (230 Kbps)
• 15-pin VGA (64 color encoding)
• Ethernet 10/100 M full/half duplex
• Two USB 2.0 compatible host connectors
• One USB 2.0 compatible target connector
• One USB OTG (On-the-Go) connector
• Expansion connector with 46 user I/Os
• 12x12 prototyping area for the integration of individual components (connections to the FPGA)
• 8x6 prototyping area for the integration of individual components (connections to the MachXO)
• Sigma Delta D/A converter
• Crimp connector with 5 signal pairs for high-speed data transfer
• Audio interface (line-in, line-out, and microphone) CODEC
• LCD connector for character displays, with contrast potentiometer
• 25 MHz oscillator with clock distribution buffer
• Eight LEDs with test points for each LED
• Two-character 7-segment display
• Green LED to indicate the proper operation of the 3.3V and 2.5 V power supplies
• Blue LED which shows the configuration status (“DONE”)
• Red LED to signal that the FPGA can be configured (“INIT”)
• Yellow LED indicating the FPGA PROGRAM# I/O is asserted (“PROGRAM#”)
• 3x4 key matrix