24
LatticeMico32/DSP Development Board
Lattice Semiconductor
User’s Guide
U10
BB3V3 IO7
FPGA Prototyping Area
T10
BB3V3 IO8
FPGA Prototyping Area
U9
BB3V3 IO9
FPGA Prototyping Area
V20
CARDSEL#
FPGA Prototyping Area
T20
CCLK
Configuration
Y21
CCLK
Configuration
U18
CFG0
Configuration
U19
CFG1
Configuration
T19
CFG2
Configuration
A10
CLK FPGA
Clock
W1
CODEC BCLK
Audio Codec
W4
CODEC CS#
Audio Codec
W2
CODEC DIN
Audio Codec
W3
CODEC DOUT
Audio Codec
AA1
CODEC LRCIN
Audio Codec
Y2
CODEC LRCOUT
Audio Codec
Y3
CODEC MCLK
Audio Codec
V4
CODEC MODE
Audio Codec
Y1
CODEC SCLK
Audio Codec
AA2
CODEC SDIN
Audio Codec
V21
CSSPIN
Configuration
U7
DAC DIG
DAC
D16
DDR A0
DDR RAM
C16
DDR A1
DDR RAM
E16
DDR A10
DDR RAM
C13
DDR A11
DDR RAM
B13
DDR A12
DDR RAM
C17
DDR A13
DDR RAM
E15
DDR A2
DDR RAM
D15
DDR A3
DDR RAM
C15
DDR A4
DDR RAM
E14
DDR A5
DDR RAM
D14
DDR A6
DDR RAM
C14
DDR A7
DDR RAM
E13
DDR A8
DDR RAM
D13
DDR A9
DDR RAM
E17
DDR BA0
DDR RAM
D17
DDR BA1
DDR RAM
A19
DDR CAS#
DDR RAM
A12
DDR CK0-
DDR RAM
B12
DDR CK0+
DDR RAM
B19
DDR CK1-
DDR RAM
A20
DDR CK1+
DDR RAM
A13
DDR CKE0
DDR RAM
Table 25. Pin Table (Continued)
Pin Name
Signal Name
Appliance