22
LatticeMico32/DSP Development Board
Lattice Semiconductor
User’s Guide
2.
Click
Select
to open the Select Device dialog box.
3.
From the Device Family drop-down list, select
FPGA Loader
. The FPGA Loader opens and displays a setup
menu in the left pane and instructions in the right pane.
4.
From the menu, select
CPLD or FPGA Device
to display the Device Configuration dialog.
5.
Click
Select
to open the Select Device dialog box. Select device family
LatticeECP
, device
LFECP33E
, and
package
484 fpBGA
from the drop-down lists.
6.
Click
OK
to return to the FPGA Loader.
7.
Click the
Browse
button under FPGA Loader Application Specific Data File and press the
Default
button to
use the standard IP provided for SPI configuration. Click
Close
to return to the FPGA Loader.
8.
Select
Fast Program
from the menu to open the data file dialog, and then select the configuration data
1
with
which you want the FPGA to be programmed.
9.
Under
Configuration Data Setup
, browse to select the programming file you wish to load into the SPI Flash.
This is the file that will ultimately be downloaded to the LFECP33E device.
10. Select
Flash Device
from the menu to open the Flash configuration dialog.
11. Under Flash Device, click
Select
. Select
SPI Serial Flash
from the drop-down menu and select
SPI-M25P80
,
STMicro
and
8-pin SOIC
. Click
OK
to return to the FPGA Loader.
12. If desired, select
Hardware Setup
to display general information about the configuration process.
13. Click
OK
to exit the FPGA Loader, add the devices and return to the ispVM System software window.
14. Click
GO
. The ispVM System software programs the SPI Flash via the FPGA.
15. Disconnect and then reconnect the power supply. The FPGA will take about three seconds to be programmed
by the SPI Flash.
Power Supply
Power is supplied via a 2.1 mm DC power jack in the top left corner of the board. The board is protected against
reversed power supply. The input supply is 5V DC.
A two-phase synchronous step-down switching regulator generates the 3.3V (1A max.) I/O voltage and the 1.2V
(2A max.) core voltage.
Note: If you use a power supply other than the one included in the shipment, make sure it supplies regulated 5V.
Reset Chip
After power-up, a power surveillance chip (U0601) waits until the 5V supply and the 3.3V I/O voltage are stable.
Then, after 200 ms, it drives the signal HPE RESET# (pin B3 of the FPGA) high. If you press the reset button, the
supervisory circuit will generate a low on the HPE RESET# signal.
The surveillance chip has an I
2
C serial 2 kbit CMOS EEPROM. The four most significant bits of the 8-bit slave
address are programmable; the default being 1010. Detailed information on the reset circuit and the I
2
C interface
can be found in the data sheet of the Catalyst Semiconductor CAT1026.
Troubleshooting
If your board is not working properly, please follow these steps for diagnosis.
1.
Usually a file with the ending .bit.
