Kortek corporation
37
of
99
PDP R&D Center
5.3.2
An Explanation of logic main board by the Block
Items
Explanation of Function
LVDS Input CONN
A Connector which RGBHV_ Data encoded from Image Board are inputted into
LED (Green) for
identifying operation
It shows that Sync and Clock are entering Logic Board normally
(Normal: flashing every second)
Key Scan input CONN
A connector for connecting
key scan Board to check and control 256K Data
EEPROM 256K
EEPROM to store Gamma Table, APC Table, Driving waveform Timing and other Options
Y-Connector
A connector to output
Y
”
driving board control signal
X-Connector
A connector to out put X
”
driving board control signal
Address
Output
A connector to output Address Data control signal with E and F-Buffer Board
Power Connnector
A connector for inputting power (5V) into Logic Board
Data Switch Blcok
Selecting internal/external signal and outputting it
Gamma Correction &
Error diffusion
Signals inputted from
Data Switch are corrected to be suitable for the property of
panel and the data are outputted into each Controller IC of RGB. Information for
input signal is outputted into APC selection block, which controls consumption
power
APC Control
It is used to select the number of sustain for sustaining discharge of 1/60 second
X-Y Switch Generator
S/W signals are made to operate driving X and Y board
’
s FET GATE and they are
outputted via Connector LX1 and LY1
Test Pattern
Patterns for the purpose of test and check are outputted
Peak Detect
Firstly, input signals have been judged. And then if low gradation signals are
inputted, sustain of unused SF (Sub Field) is removed to reduce LOAD of driving
FET
Diffusion Filter
An algorism of being used to reduce false contouring
Sub Field Generator
It converts data which are being inputted in
Subfield Weight Sequence
(12 Subfields)
Sub Field Matrix
It uses 16*16 Array to group, by Subfield Weight, data which are inputted in
Subfield Weight Sequence
SGRAM Controller
After
it writes data grouped by Subfield Weight to memory, it gets input of SF_ID
and reads data from memory to output into Rearrangement Block
REARRANGE
After data read from Memory are rearranged to be suitable for input FORMAT of
DATA driver IC (COF or COB (VGA PDP having resolution of 852*480), DATA are
outputted to E and F-Buffer Board
Содержание P42SV
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