Kortek corporation
36
of
99
PDP R&D Center
5.3 Logic Part
5.3.1 Block Diagram and Configuration of Logic MAIN Board
Test Pattern
Data Switch
Gamma(GTS)
SFGEN
1V Delay
Diff Filter
Error Diff
Gain Control
SF
Matrix
Peak Detect
ASL Detect
APC Control
Fix APC
I/F Control
Ycon
Xcon
XY
Buffer
Mem
Control
Rear-
range
Address driver IC
Control signal
RGB Data
X,Y driver FET Control Signal
Scan driver IC Control Signal
Scan Data
32M
32M
32M
32M
I/F Control
EEPROM 256K
60MHz
40MHz
28.63MHz
Fix APC
Fix APC
X
_l
o
g
ic
S
ig
n
a
l
O
u
tp
u
t
C
o
n
n
e
c
to
r
A
d
d
re
s
s
L
o
g
ic
S
ig
n
a
l
O
u
tp
u
t
C
o
n
n
c
to
r
Y_logic Signal
Output Connector(LY)
Address Logic
Output Signal
Buffer IC
60M
Data Clock
Generator 60MHz
Data Memory Controller
IC
2
0
3
1
R
e
g
u
la
tr
o
(3
.3
V
)
L
D
1
C
N
2
0
0
L
A
0
3
LVDS Input
Connector
Inside/Outside
Select-switch
Logic Power
Input Connector
NTSC/PAL Select-switch
Inside/Outside
Select-switch
NTSC/PAL Select-switch
LK1
NTSC/PAL select
(CN2002)
Inside/
Outside
(CN2001)
LED
(LD2001)
A
d
d
re
s
s
L
o
g
ic
S
ig
n
a
l
O
u
tp
u
t
C
o
n
n
c
to
r
Содержание P42SV
Страница 2: ...Kortek co kr May 2003 Printed in korea...
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