Kortek corporation
38
of
99
PDP R&D Center
5.3.2(A) Test Pattern Generator
(1) Block configuration diagram
TEST PATTERN GENERATER
TH_SYNC_OT
TV_SYC_OT
SEL[3...0] TRED_OUT[7...0]
nRESET TGRN_OUT[7
…
0]
CLK26 TBLU_OUT[7
…
0]
(2) Descriptions of block
’
s functions
■ Generates H, V SYNC for testing
■ Generates the test pattern using SEL_in[3..0] as Select signals(R[7..0], G[7...0], B[7..0])
5.3.2(B) Data Switch
DATA_SWITCH
TH_SYNC_OT
TV_SYNC_OT
TRED_OUT[7..0]
TGRN_OUT[7..0] H_SYNC_OUT
TBLU_OUT[7..0] V_SYNC_OUT
H_SYNC
V_SYNC RED_OUT[7..0]
GRN_OUT[7..0]
RED_IN[7..0] BLU_OUT[7..0]
GRN_IN[7..0] CLK13_OUT
BLU_IN[7..0] AREA_OT
DATA_SW_ID
nRESET
CLK26
1. Internal test pattern path
2. Scaler board
’
s pattern path
Содержание P42SV
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