Kortek corporation
32
of
99
PDP R&D Center
5.2.3 Analysis of Driving Pulse
5.2.4 Principles of FET’s Operation and High Voltage Switching
■ FET
’
s operation principles
1) With signal impressed on the gate(Positive voltage),
FET gets short-circuited(a conduting wire of zero(0)
Resistance):and
2) With no signal impressed on the gate (GND), FET
gets open-cricuited(a non-conducting wire of ∞
resistance).
■ FET
’
s high voltage switching principles
(-)(-)(-)(-)
(-)(-)
Vs:165V
Wall Charge
(-)(-)
(+)(+)
X_rising 190V
(-)(-)
(-)(-)
(-)(-)
(+)(+)
(+)(+)
Va:70V
(+)(+)(+)(+)
RESET Period
SCAN Period
SUSTAIN Period
Owing to the piled elctric
-charge, second
discharge happen.
The weak discharge(in case of
raise the voltage under unusual
case) pile up electric-charges
until discharge just begin.
Though voltage is down,
electric-charges is not
extinct.
Select the cell to display for sustain period.
Y
X
Address
The cells is more reliably
selected within sustain
period
(+)(+)
weak discharge
strong
discharg
e
D
G:
Gate
S:
Source
D:
Drain
G
S
P u l s e O u t p u t ( 1 8 0 V p - p )
G A T E S I G N A L ( 1 5 V p - p )
1 ) w i t h n o s i g n a l i m p r e s s e d o n G 1 F E T 1 g e t s o p e n - c irc u ite d , a n d w ith s i g n a l i m p r e s s e d o n G 2 , F E T 2 g e t s
s h o r t - c i r c u i t e d , t h e r e b y c a u s i n g G N D to b e o u t p u t t e d t o o u t p u t t e r m inals
2 ) W ith s i g n a l i m p r e s s e d o n G 1 , F E T 1 g e t s s h o r t - c i r c u i t e d , a n d w i t h n o s i g n a l i m p r e s s e d o n G 2 , F E T 2 g e t s
o p e n - c irc u ite d , t h e r e b y c a u s i n g 1 8 0 V t o b e o u t p u t t e d t o o u t p u t t e r m inals
G 1
G 2
1 8 0 V
F E T 1
F E T 2
G N D
Содержание P42SV
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