Keysight Technologies 16860 Series, Руководство по обслуживанию

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Keysight 16860 Series Portable Logic Analyzers Service Guide 91
Troubleshooting 5
Logic Acquisition Self-Test Descriptions
The self-tests for the logic analyzer identify the correct operation of major functional areas in the
module.
Interface FPGA Version Test
This test verifies that the FPGA program is a version that the software can use. This is necessary
because new features will be added to the 16860 logic analyzer that will require both new software
and new FPGA bits.
Interface FPGA Register Test
The purpose of this test is to verify that the backplane interface can communicate with the backplane
FPGA. The FPGA must be working before any of the other circuits on the board will work. Also, the
FPGA generates the board ID code that is returned to identify the module and slot.
FPGA to FPGA Communication Test
This test is only run if there are two or more logic analyzer installed and connected together with the
flex cables. The purpose of this test is to verify that the FPGAs can drive and receive the signals
correctly.
SPI Bus Communication Test
The purpose of this test is to verify communications over the SPI bus from the Interface FPGA to
various devices attached to the SPI bus.
EEPROM Test
The purpose of this test is to verify:
• The address and data paths to the EEPROM.
• That each cell in the EEPROM can be programmed high and low.
• That individual locations can be independently addressed.
• The EEPROM can be block erased.
Probe ID Read Test
The purpose of this test is to verify that the Probe ID values can be correctly read and to verify the
functionality of the Digital to Analog Converter by testing the two Probe ID DAC outputs at various
voltage levels.
Chip Registers Read/Write Test
The purpose of this test is to verify that each bit in each register of the Analysis chip can be written
with a 1 and 0 and read back again. The test also verifies that a chip reset sets all registers to their
reset condition (all 0s for most registers).
Freq Synth Lock Detect Test
This test determines if all the voltage-controlled oscillators (VCOs) are working properly.
Acquisition Chip BIST Test
Tests the Timing Zoom memory and other internal memories on the acquisition chip.
Resource Bus Connection Test
The purpose of this test is to verify global resources.