REL1.0
Page 16 of 58
iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
77
USB_OTG_ID
O, 3.3V CMOS
USB OTG ID input for USB host or device
detection.
This pin is connected from Micro USB OTG
connector (J4).
78
USB_PWR_EN
I, 3.3V CMOS
USB active high power enable output to control
external USB Vbus.
This pin is connected to USB OTG Power switch
enable pin to control USB OTG VBUS power.
79
GND
Power
Ground.
80
PL_IO_L3P_T0_DQS_PUDC
_B_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
Note: Optionally this pin is connected to J15
th
pin
of FMC connector (J1) through resistor and default
not populated.
81
USB_OTG_DP
IO, DIFF
USB OTG data positive.
This pin is connected to Micro USB OTG connector
(J4).
82
NC
NA
NC.
83
USB_OTG_DM
IO, DIFF
USB OTG data negative.
This pin is connected to Micro USB OTG connector
(J4).
84
NC
NA
NC.
85
NC
NA
NC.
86
PL_IO_L9P_T1_DQS_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H19
th
pin of FMC
connector (J1).
87
NC
NA
NC.
88
VIN_3V3
O, 3.3V Power
Supply Voltage.
89
PL_IO_L9N_T1_DQS_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H20
th
pin of FMC
connector (J1).
90
PL_IO_L12P_T1_MRCC_34
O, 3.3V LVCMOS
Bank34 Clock user Multi region positive Single
ended pin.
This pin is connected to H4
th
pin of FMC
connector (J1).
91
PL_IO_L19P_T3_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to 1
st
pin of Pmod
connector2 (J5).
Note: Optionally this pin is connected to F16
th
pin
of FMC connector (J1) through resistor and default
not populated.
