Technical Reference
Dual-Core Intel® Xeon® Processor LV and Intel
®
3100 Chipset
User’s Manual
January 2007
38
Order Number:315879-002
3.0
Technical Reference
3.1
Memory Resources
Detailed memory information for addressable memory and memory maps can be found
in the
Intel
®
3100 Chipset External Design Specification
.
3.2
DMA Channels
The DMA Channels below specify Partial DMA channels that are routed to specific
devices as well as other channels that are available.
3.3
Fixed I/O Map
Refer to the
Intel
®
3100 Chipset External Design Specification
for this information.
3.4
Interrupts
Interrupts can be routed through the I/O xAPIC and supports a total of 24 interrupts.
The I/O xAPIC is supported by Microsoft Windows XP*.
Table 10 on page 39
provides
the interrupts and there correlating functions.
Table 9.
DMA Channels
Data Channel
Data Width
System Resource
0
8
Open
1
8
Parallel Port
2
8
Diskette Drive
3
8
Parallel Port (for ECP or EPP)
4
8 or 16 bits
DMA Controller
5
16 bits
Open
6
16 bits
Open
7
16 bits
Open
