Dual-Core Intel® Xeon® Processor LV and Intel
®
3100 Chipset
January 2007
User’s Manual
Order Number: 315879-002
39
Technical Reference
3.5
PCI Conventional Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected
between the PCI Conventional bus connectors and on-board PCI Conventional devices.
The PCI Conventional specification describes how interrupts can be shared between
devices attached to the PCI Conventional bus. In most cases, the small amount of
latency added by interrupt sharing does not affect the operation or throughput of the
devices. In some special cases where maximum performance is needed from a device,
a PCI Conventional device should not share an interrupt with other PCI Conventional
devices. Use the following information to avoid sharing an interrupt with a PCI
Conventional add-in card.
Table 10.
I/O x APIC Interrupts
IRQ
System Resource
NMI
I/O channel check
0
Reserved, interval timer
1
Reserved, keyboard buffer full
2
Reserved, cascade input from slave PIC
3
User available
4
COM1
1
5
User available
6
Diskette drive
7
LPT1
1
8
Real-time clock
9
User available
10
User available
11
User available
12
On-board mouse port (if present, else available)
13
Reserved, math coprocessor
14
Primary Serial ATA
15
Secondary Serial ATA
16
User available (through PIRQA)
2
17
User available (through PIRQB)
2
18
User available (through PIRQC)
2
19
User available (through PIRQD)
2
20
User available (through PIRQE)
2
21
User available (through PIRQF)
2
22
User available (through PIRQG)
2
23
User available (through PIRQH)
2
Notes:
1.
Default but can be changed to another IRQ.
2.
Available in APIC mode only.
