Intel PXA270, Руководство по оптимизации

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3-2 Intel® PXA27x Processor Family Optimization Guide
System Level Optimization
•
Setting wait-states for static memory
For static memory, it is important to use the correct number of wait-states to get optimal
performance. The Intel® PXA27x Processor Family Developer’s Manual explains the
possible values in the MSCx registers. These registers control wait states and set up the access
mode used. For flash memory that supports burst-of-four reads or burst-of-eight reads, these
modes provide improvements in reading and executing from flash.
•
CAS latency for SDRAM
For SDRAM the key parameter is the CAS latency. Lower CAS latency gives higher
performance. Most current SDRAM supports a CAS latency of two
•
Setting of the APD bit
Use of the APD bit in the memory controller can save power, however can also increase the
memory latency. For high performance the APD bit should be cleared.
•
Buffer Strength registers
The output drivers for the PXA27x processor external memory bus have programmable
strength settings. This feature allows for simple, software-based control of the output driver
impedance for the external memory bus. Use these registers to match the driver strength of the
PXA27x processor to external memory bus. The buffer strength should be set to the lowest
possible setting (minimum drive strength) that still allows for reliable memory system
performance. This will minimize the power usage of the external memory bus, which is a
major component of total system power. Refer to the Programmable Output Buffer Strength
registers described in the
Intel® PXA27x Processor Family Developer’s Manual , for more
information.
3.2.2 Alternate Memory Clock Setting
An alternate set of memory bus selections are available through the use of CCCR[A], refer to the
“CCCR Bit Definitions” table in the Intel® PXA27x Processor Family Developer’s Manual . When
this bit is set the memory clock speed is expanded to allow it to be set as high as 208 MHz. When
cleared the maximum memory clock speed is 130 MHz.
If CCCR[A] is cleared, use the “Core PLL Output Frequencies for 13-MHz Crystal with CCCR[A]
= 0” table in the Intel® PXA27x Processor Family Developer’s Manual when making the clock
setting selections. If CCCR[A] is set, use the “Core PLL Output Frequencies for 13-MHz Crystal
Table 3-2. Internal SRAM Access Latency and Throughput for Different Frequencies (Silicon
Measurement Pending)
Core Clock
Speed (MHz)
(up to)
Run Mode
Frequency (MHz)
(up to)
System Bus Clock
Speed (MHz)
(up to)
Memory
Clock Speed
(MHz)
(up to)
Memory
Latency
(core cycles)
Load
Throughput
from Memory
(MBytes/
Sec)
†
104 104 104 104 14 236
208 208 208 104 14 472
312 208 208 104 21 473
† Store throughput is similar