Intel PXA270, Руководство по оптимизации

Страница: 21 / 144

Intel® PXA27x Processor Family Optimization Guide 2-1
Microarchitecture Overview
2
2.1 Introduction
This chapter contains an overview of Intel XScale® Microarchitecture and Intel® Wireless
MMX™ Technology. The Intel XScale® Microarchitecture includes a superpipelined RISC
architecture with an enhanced memory pipeline. The Intel XScale® Microarchitecture instruction
set is based on ARM* V5TE architecture; however, the Intel XScale® Microarchitecture includes
new instructions. Code developed for the Intel® StrongARM* SA-110 (SA-110), Intel®
StrongARM* SA-1100 (SA-1100), and Intel® StrongARM* SA-1110 (SA-1110) microprocessors
is portable to Intel XScale® Microarchitecture based processors. However, to obtain the maximum
performance, the code should be optimized for the Intel XScale® Microarchitecture using the
techniques presented in this document.
2.2 Intel XScale® Microarchitecture Pipeline
This section provides a brief description of the structure and behavior of Intel XScale®
Microarchitecture pipeline.
2.2.1 General Pipeline Characteristics
The following sections discuss general pipeline characteristics.
2.2.1.1 Pipeline Organization
The Intel XScale® Microarchitecture has a 7-stage pipeline operating at a higher frequency than its
predecessors allowing for greater overall performance. The Intel XScale® Microarchitecture
single-issue superpipeline consists of a main execution pipeline, a multiply-accumulate {MAC}
pipeline, and a memory access pipeline.
Figure 2-1 shows the pipeline organization with the main
execution pipeline shaded.
Figure 2-1. Intel XScale® Microarchitecture RISC Superpipeline
F1 F2 ID RF X1 X2 XWB
M1 M2 Mx
D1 D2 DWB
Main execution pipeline
MAC pipeline
Memory pipeline