Intel PXA270, Руководство по оптимизации

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Intel® PXA27x Processor Family Optimization Guide 3-3
System Level Optimization
With B=0 and CCCR[A] = 1” table and the “Core PLL Output Frequencies for 13 MHz Crystal
With B=1 and CCCR[A] = 1” table in the Intel® PXA27x Processor Family Developer’s Manual
instead.
3.2.3 Page Table Configuration
Three bits for each page are used to configure each memory page’s cache behavior. Different
values of X,C,B determine the caching, reading and writing, and buffering policies of the pages.
3.2.3.1 Page Attributes For Instructions
When examining these bits in a descriptor, the instruction cache only utilizes the C bit. If the C bit
is clear, the instruction cache considers a code fetch from that memory to be noncacheable, and will
not fill a cache entry. If the C bit is set, then fetches from the associated memory region is cached.
3.2.3.2 Page Attributes For Data Access
For data access, all three attributes are important. If the X bit for a descriptor is zero, the C and B
bits operate as defined by the ARM* architecture. This behavior is detailed in Table 3-3 .
If the X bit for a descriptor is one, the C and B bits behave differently, as shown in Table 3-4 . The
load and store buffer behavior in Intel XScale® Microarchitecture is explained in Section 2.2.4.1.1,
“Write Buffer Behavior” and Section 2.2.4.1.2, “Read Buffer Behavior”
Table 3-3. Data Cache and Buffer Behavior when X = 0
C B Cacheable?
Load Buffering
and Write
Coalescing?
Write Policy
Line Allocation
Policy
Notes
0 0 N N
— —
Stall until complete
†
0 1 N Y
— —
1 0 Y Y Write-through Read Allocate
1 1 Y Y Write-back Read Allocate
†
Normally, the processor continues executing after a data access if no dependency on that access is
encountered. With this setting, the processor stalls execution until the data access completes. This
guarantees to software that the data access has taken effect by the time execution of the data access
instruction completes. External data aborts from such accesses are imprecise.
Table 3-4. Data Cache and Buffer Behavior when X = 1 (Sheet 1 of 2)
C B Cacheable?
Load Buffering
and Write
Coalescing?
Write Policy
Line Allocation
Policy
Notes
0 0 — — — — Unpredictable -- do not use
0 1 N Y — —
Writes will not coalesce into
buffers
†