Intel PXA270, Руководство по оптимизации

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Intel® PXA27x Processor Family Optimization Guide A-1
Performance Checklist A
A.1 Performance Optimization Tips
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Use fast 100-MHz SDRAM with a CAS latency of 2
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Use flash that supports read bursts of four or eight
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Optimize flash and SDRAM timings
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Don't set the LCD refresh higher than required
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When possible, use DMA in device drivers instead of programmed I/O to load/unload FIFO's
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Use interrupts, avoid polling, and frequent interrupts
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Lock cache lines and TLB entries for frequently used operations
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Make sure the instruction and data caches are enabled
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Use cache policies to optimize throughput and performance
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Use the internal SRAM
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Park the system bus arbiter on the Intel XScale® core unless performing task which heavily
uses a different system bus client
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Make the LCD frame buffer non-cached but bufferable
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Use write-back caches if possible
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Optimize assembly code based on the suggestions presented in this guide
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Enable the branch target buffer
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Configure non cacheable memory as bufferable whenever possible
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Choose a fast run mode speed for minimal memory latency and a fast turbo mode for
processing speed
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Optimize data loads with the PLD instruction and data stores with code that encourages write
coalescing
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Choose a V5TE compiler optimized for Intel XScale® Microarchitecture
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Use the optimized Intel® Integrated Performance Primitives
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Enable the Intel® Wireless MMX™ Technology media co-processor
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Include all necessary software hooks for Intel VTune™ environment
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Use LCD color conversion hardware for video applications
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Use fast-bus mode for high system-bus bandwidth
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Use alternate memory clock setting for high memory bus throughput
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Ensure that the latest board support package is being used
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Use Intel® Quick Capture Interface for image data