6-2
Intel® PXA27x Processor Family
Optimization Guide
Power Optimization
6.2.2.2
Idle Mode
This mode is the same as normal mode except the clocks to the CPU are disabled. Recovery is
through the assertion of interrupts.
6.2.2.3
Deep Idle Mode
This mode is the same as idle mode except the system bus and all controllers connected to it,
operate at 13 MHz. This results in lower power consumption than idle mode. The system bus will
have very limited bandwidth available in deep idle mode since it operates at 13 MHz - verify that
the system bus bandwidth at 13 MHz is sufficient before implementing deep idle mode.
Also consider whether peripherals clocked from the core PLL (see
“Clocks Manager and Clocks
Distribution Block Diagram”
in the
Intel® PXA27x Processor Family Developer’s Manual
) can
properly operate with a 13-MHz clock. For example, the LCD panel might not be able to be
refreshed without artifacts using a 13MHz clock.
Deep idle mode allows CCCR[PPDIS] to remain cleared (CCCR[CPDIS] is always set in deep idle
mode). This allows the peripheral units clocked from the peripheral PLL to run at their normal
operating frequencies, resulting in these peripherals operating normally. Consideration must be
given to the system bus however, which is limited to 13-MHz operation. The bandwidth
requirements of the entire system (including all peripherals and LCD controller) cannot exceed the
bandwidth available on the system bus.
6.2.2.4
Standby Mode
All power domains except VCC_RTC, and VCC_OSC are placed in a low-power mode where state
is retained but no activity is allowed, some of the internal power domains (see the
Intel® PXA270
Processor Electrical, Mechanical, and Thermal Specification
and the
Intel® PXA27x Processor
Family Electrical, Mechanical, and Thermal Specification
) can be powered off, and both PLLs are
disabled; recovery is through external and select internal wake-up events.
6.2.2.5
Sleep Mode
All internal power domains except the VCC_RTC, and VCC_OSC (see the
Intel® PXA270
Processor Electrical, Mechanical, and Thermal Specification
and the
Intel® PXA27x Processor
Family Electrical, Mechanical, and Thermal Specification
) can be powered down, all clock
sources except to the real time clock and power manager are disabled, and the external-low-
voltage-power supplies can be disabled; the remaining power domains are placed in a low-power
state where state is retained but no activity is allowed; recovery is through external and select
internal wake-up events and recovery requires a system reboot to recover since the program
counter is invalid.
6.2.2.6
Deep-Sleep Mode
All internal power domains except the VCC_RTC (real time controller) and VCC_OSC
(OScillator) can be powered down, all clock sources except to the real time clock and power
manager are disabled, and the external low-voltage and high-voltage power supplies can be
disabled; all power domains are powered directly from the backup battery pin VCC_BATT; the
remaining power domains are placed in a low-power state where state is retained but no activity is
allowed; recovery is through external and select internal wake-up events and recovery requires a
system reboot to recover since the program counter is invalid.
Содержание PXA270
Страница 1: ...Order Number 280004 001 Intel PXA27x Processor Family Optimization Guide April 2004...
Страница 10: ...x Intel PXA27x Processor Family Optimization Guide Contents...
Страница 20: ...1 10 Intel PXA27x Processor Family Optimization Guide Introduction...
Страница 30: ...2 10 Intel PXA27x Processor Family Optimization Guide Microarchitecture Overview...
Страница 48: ...3 18 Intel PXA27x Processor Family Optimization Guide System Level Optimization...
Страница 114: ...5 16 Intel PXA27x Processor Family Optimization Guide High Level Language Optimization...
Страница 122: ...6 8 Intel PXA27x Processor Family Optimization Guide Power Optimization...
Страница 143: ...Intel PXA27x Processor Family Optimization Guide Index 5 Index...
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