Intel PXA270, Руководство по оптимизации

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Intel® PXA27x Processor Family Optimization Guide 1-5
Introduction
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Superset of existing Intel XScale® Microarchitecture media processing instructions
See the Intel® Wireless MMX™ technology Coprocessor EAS for more details.
1.2.4 Memory Architecture
1.2.4.1 Caches
There are two caches:
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Data cache – The PXA27x processor supports 32 Kbytes of data cache.
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Instruction Cache – The PXA27x processor supports 32 Kbytes of instruction cache.
1.2.4.2 Internal Memories
The key features of the PXA27x processor internal memory are:
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256 Kbytes of on-chip SRAM arranged as four banks of 64 Kbytes
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Bank-by-bank power management with automatic power management for reduced power
consumption
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Byte write support
1.2.4.3 External Memory Controller
The PXA27x processor supports a memory controller for external memory which can access:
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SDRAM up to 100 MHz at 1.8 Volts.
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Flash memories
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Synchronous ROM
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SRAM
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Variable latency input/output (VLIO) memory
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PC card and compact flash expansion memory
1.2.5 Processor Internal Communications
The PXA27x processor supports a hierarchical bus architecture. A system bus supports high
bandwidth peripherals, and a slower peripheral bus supports peripherals with lower data
throughputs.
1.2.5.1 System Bus
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Interconnection between the major key components is through the system bus.
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64-bit wide, address and data multiplexed bus.
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The system bus allows split transactions, increasing the maximum data-throughput in the
system.
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Different burst sizes are allowed; up to 4 data phases per transactions (that is, 32 bytes). The
burst size is set in silicon for each peripheral and is not configurable.