Intel® Compute Module MFS5520VI TPS
Functional Architecture
Revision 1.5
15
Intel order number: E64311-007
socket 2 are mutually independent. As a result, if channel A and channel B have identical DIMM
population, and if channel D and channel E have identical DIMM population, then mirroring
is possible.
For example, if the system is populated with six DIMMS {A1, B1, A2, B2, D1, E1}, channel
mirroring is possible. Both the populations shown in the following table are valid.
Table 3. Mirroring DIMM Population Rules Variance across Nodes
A1
A2
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
Mirroring
Possible?
P
P
P
P
Yes
P
P
P
P
P
P
Yes
3.2.5
Memory Upgrade Rules
Upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the
following factors:
Current RAS mode of operation
Existing DDR3 DIMM population
DDR3 DIMM characteristics
Optimization techniques used by the Intel
®
Xeon
®
Processor 5500 series and Intel
®
Xeon
®
Processor 5600 series to maximize memory bandwidth
In the Channel Independent mode, all DDR3 channels operate independently. The Channel
Independent mode can also be used to support a single DIMM configuration in channel A and in
the single channel mode.
The following general rules must be observed when selecting and configuring memory to obtain
the best performance from the system.
Mixing RDIMMs and UDIMMs is not supported.
Mixing memory type, size, speed, rank and/or vendors in the compute module is
not supported.
Non-ECC memory is not validated and is not supported in a server environment.
Use of identical DIMMs in the compute module is recommended.
If an installed DDR3 DIMM has faulty or incompatible SPD data, it is ignored during
memory initialization and is (essentially) disabled by the BIOS. If a DDR3 DIMM has no
or missing SPD information, the slot in which it is placed is treated as empty by
the BIOS.
When CPU Socket 1 is empty, any DIMM memory in Channel A through Channel C
is unavailable.
When CPU Socket 2 is empty, any DIMM memory in Channel D through Channel F
is unavailable.
If both processor sockets are populated but Channel A through Channel C is empty, the
platform can still function with remote memory in Channel D through Channel F.
However, platform performance suffers latency due to remote memory.
